J.A.G. Jess

IC spot-defect and fault semantics-a unified framework

J. Pineda de Gyvez, J.A.G. Jess, 1990, IEEE International Symposium on Circuits and Systems.

High-level synthesis scheduling and allocation using genetic algorithms based on constructive topological scheduling techniques

J.A.G. Jess, M.J.M. Heijligers, 1995, Proceedings of 1995 IEEE International Conference on Evolutionary Computation.

An improvement of a fast and accurate CMOS bridging fault simulator

J.A.G. Jess, C. Di, 1995 .

Low power PLAs

M.R.C.M. Berkelaar, J.A.G. Jess, da R. Nobrega Tavares, 1998 .

On the definition of critical areas for IC photolithographic spot defects

J. Pineda de Gyvez, J.A.G. Jess, J. Jess, 1989, [1989] Proceedings of the 1st European Test Conference.

Synthesis of concurrent hardware structures

J.A.G. Jess, L. Stok, R. v.d. Born, 1988, 1988., IEEE International Symposium on Circuits and Systems.