Fumio Ootsuka

A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC's

K. Mori, Kenichi Kikushima, Fumio Ootsuka, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Front-End Process Technology for hp65/45 CMOS Devices

Kunio Nakamura, Yasuo Nara, Fumio Ootsuka, 2006 .

Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning

Kikuo Yamabe, Yasuo Nara, Kenji Shiraishi, 2006 .

Reliable Extractions of EOT and Vfb in Poly-Si Gate High-k MISFETs through Advanced Modeling of Gate and Substrate Capacitances

A. Toriumi, Tsuyoshi Horikawa, Naoki Yasuda, 2005 .