Ya-Chin King

发表

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology

Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, 2019, Sensors.

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed

Meng-Fan Chang, Huazhong Yang, Yongpan Liu, 2017, IEEE J. Solid State Circuits.

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

Meng-Fan Chang, Huazhong Yang, Yongpan Liu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

On-chip trimming circuit based on embedded one-time-programming memory for magnetic wireless interlayer transmission module

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2015 .

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

Rich Liu, Ya-Chin King, Yi-Hsuan Hsiao, 2009, IEEE Transactions on Electron Devices.

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

Yue-Der Chih, Jonathan Chang, Ya-Chin King, 2019, Integr..

Variable-length gateless transistor for analog one-time-programmable memory applications

Ya-Chin King, Chrong Jung Lin, Po-Ruei Cheng, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

Ya-Chin King, Chrong Jung Lin, Chiu-Wang Lien, 2011, IEEE Electron Device Letters.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2009, IEEE Transactions on Electron Devices.

Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2010, 2010 International Electron Devices Meeting.

Statistical analysis of the correlations between cell performance and its initial states in contact resistive random access memory cells

Ya-Chin King, Chrong Jung Lin, Yun Feng Kao, 2017 .

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Meng-Fan Chang, Wei-Hao Chen, Yen-Cheng Chiu, 2020, IEEE Journal of Solid-State Circuits.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2013, IEEE Journal of Solid-State Circuits.

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

Ming-Jinn Tsai, Ya-Chin King, Shyh-Shyuan Sheu, 2012, 2012 International Electron Devices Meeting.

Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2010, 2010 International Electron Devices Meeting.

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Meng-Fan Chang, Qi Wei, Huazhong Yang, 2017, IEEE Journal of Solid-State Circuits.

Punchthrough diode as the transient voltage suppressor for low-voltage electronics

Ya-Chin King, Chenming Hu, Bin Yu, 1996 .

A four transistor CMOS active pixel sensor with high dynamic range operation

Ya-Chin King, Cheng-Hsiao Lai, Che-I Lin, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM

Ya-Chin King, Liang-Shun Chang, Chrong-Jung Lin, 2013, IEEE Electron Device Letters.

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

Meng-Fan Chang, Tzu-Hsiang Hsu, Ren-Shuo Liu, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A Resist-Protection-Oxide Transistor With Adaptable Low-Frequency Noise for Stochastic Neuromorphic Computation in VLSI

Jeng Gong, Ya-Chin King, Hsin Chen, 2011, IEEE Electron Device Letters.

3D time-contingent physical unclonable function array on 16nm FinFET dielectric RRAM

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

Dummy Read Scheme for Lifetime Improvement of MLC NAND Flash Memories

Ya-Chin King, Chrong-Jung Lin, Dai Yan Wu, 2016, IEEE Transactions on Device and Materials Reliability.

Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies

Ya-Chin King, Chrong Jung Lin, Chieh Lee, 2019, 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

New Bi-Directional Tunneling Program/Erase AND Flash Memory for Multi-Level Storage Applications

Vincent Huang, Evans Ching-Song Yang, Charles Ching-Hsiang Hsu, 2003 .

Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) Cell and read-disturb-free temperature-aware current-mode read scheme

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2013, 2013 Symposium on VLSI Circuits.

Gate stress effect on low temperature data retention characteristics of split-gate flash memories

Ya-Chin King, Kenneth Wu, Ling-Chang Hu, 2005, Microelectron. Reliab..

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

Chih-Cheng Lu, Jeng Gong, Ya-Chin King, 2011, IEEE Electron Device Letters.

Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory

Ya-Chin King, Shih-Chen Wang, Kung-Hong Lee, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

Mapping of wafer-level plasma induced charge contour by novel on-chip in-situ recorders in advance FinFET technologies

Ya-Chin King, Chrong Jung Lin, Chun-Hsiung Wu, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Meng-Fan Chang, Shu-Meng Yang, Che-Wei Wu, 2012, 2012 IEEE International Solid-State Circuits Conference.

Twin mode NV logic gates for high speed computing system on 16nm FINFET CMOS logic process

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2011, IEEE Transactions on Electron Devices.

A Body Effect Assisted NOR-Type (BeNOR) Multilevel Flash Memory

Evans Ching-Song Yang, Charles Ching-Hsiang Hsu, Ya-Chin King, 2000 .

A novel single poly-silicon EEPROM using trench floating gate

Ya-Chin King, Meng-Yi Wu, Shin-Chang Feng, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yu Wang, Meng-Fan Chang, Qi Wei, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications

Meng-Fan Chang, Yu-Der Chih, Ya-Chin King, 2017, 2017 Symposium on VLSI Circuits.

A Study of Read Variability in Backfill Contact Random Access Memory

Ya-Chin King, Chrong-Jung Lin, Fu-Cheng Chang, 2020, 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory

Amy Hsiu-Fen Chou, Evans Ching-Song Yang, Charles Ching-Hsiang Hsu, 2000 .

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Meng-Fan Chang, Frederick T. Chen, Ming-Jinn Tsai, 2014, IEEE Journal of Solid-State Circuits.

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

Meng-Fan Chang, Wu-Chin Tsai, Yu-Der Chih, 2015, IEEE Transactions on Electron Devices.

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

Meng-Fan Chang, Che-Wei Wu, Yu-Der Chih, 2013, IEEE Journal of Solid-State Circuits.

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

Ya-Chin King, Chrong Jung Lin, Meng-Yin Hsu, 2017, Nanoscale Research Letters.

Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Reliability evaluation of Gilbert cell mixer based on a hot-carrier stressed device degradation model

Ya-Chin King, Wei-Cheng Lin, Long-Jei Du, 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell

Meng-Fan Chang, Tien-Fu Chen, Ya-Chin King, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Frederick T. Chen, Ming-Jinn Tsai, Yue-Der Chih, 2013, IEEE Electron Device Letters.

Self-convergent scheme for logic-process-based multilevel/analog memory

Ya-Chin King, Shih-Chen Wang, Kung-Hong Lee, 2005 .

Reliability evaluation of 5.2GHz CMOS receiver

Ya-Chin King, Wei-Cheng Lin, 2005, 2005 European Microwave Conference.

A 0.26-$\mu\hbox{m}^{2}$ U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology

Ya-Chin King, Han-Chao Lai, Chrong-Jung Lin, 2007, IEEE Electron Device Letters.

A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate

Yue-Der Chih, Ya-Chin King, Kai-Chun Lin, 2009, IEEE Electron Device Letters.

Multi-channel magnetic transmission interface for 3D contactless connection

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Chih-Yuan Lu, Ya-Chin King, Hang-Ting Lue, 2016, IEEE Transactions on Electron Devices.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Meng-Fan Chang, Sreedhar Natarajan, Yu-Der Chih, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs

Hung-Yu Chen, Ya-Chin King, Chrong Jung Lin, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Chih-Yuan Lu, Ya-Chin King, Hang-Ting Lue, 2015, IEEE Electron Device Letters.

An investigation of program disturb characteristics and data pattern effect in 128G 3D NAND flash memories

Yu-Hung Yeh, Ya-Chin King, Chrong-Jung Lin, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation

Meng-Fan Chang, Yu-Der Chih, Ya-Chin King, 2019, IEEE Journal of Solid-State Circuits.

Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell

Charles Ching-Hsiang Hsu, Ya-Chin King, Meng-Yi Wu, 2006 .

A New Antifuse Cell With Programmable Contact for Advance CMOS Logic Circuits

Chia-En Huang, Ya-Chin King, Chrong-Jung Lin, 2008, IEEE Electron Device Letters.

Built-In Self-Repair for Die-to-Die Misalignment of Multidie Space Sensors

Shi-Yu Huang, Ya-Chin King, Chun-Fu Chen, 2007, IEEE Sensors Journal.

24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Meng-Fan Chang, Albert Lee, Ya-Chin King, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Investigation of Set/Reset Operations in CMOS-Logic-Compatible Contact Backfilled RRAMs

Hung-Yu Chen, Ya-Chin King, Chrong Jung Lin, 2016, IEEE Transactions on Device and Materials Reliability.

Invited Talk 1

Ya-Chin King, 2009 .

Multilevel Anti-Fuse Cells by Progressive Rupturing of the High- $\kappa $ Gate Dielectric in FinFET Technologies

Ya-Chin King, Chrong Jung Lin, Yu-Zheng Chen, 2016, IEEE Electron Device Letters.

Reliability Evaluation and Redesign of LNA

Ya-Chin King, Wei-Cheng Lin, Long-Jei Du, 2004, Microelectron. Reliab..

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Meng-Fan Chang, Yen-Chen Liu, Yu-Der Chih, 2015, IEEE Journal of Solid-State Circuits.

Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion

Shi-Yu Huang, Ya-Chin King, Shih-Fang Chen, 2005, IEEE Transactions on Consumer Electronics.

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Ya-Chin King, Chun-Yu Chuang, Chrong-Jung Lin, 2021 .

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

Ya-Chin King, Min-Che Hsieh, Yung-Wen Chin, 2015, IEEE Journal of the Electron Devices Society.

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

Ya-Chin King, Hsien-Chun Chang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

New Coupling Ratio Extraction Method for Split Gate Flash Memory

Amy Hsiu-Fen Chou, Evans Ching-Song Yang, Ya-Chin King, 2000 .

A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory

Rich Liu, Ya-Chin King, Tzu-Hsuan Hsu, 2007, IEEE Electron Device Letters.

Twin-bit Via RRAM in 16nm FinFET Logic Technologies

Ya-Chin King, Chrong Jung Lin, Y.-H. Shih, 2017 .

Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split $C$–$V$ Method to Specifically Characterize the STI Stress Effect Along the Width Direction of MOSFET Devices

Yao-Wen Chang, Ya-Chin King, Chih-Yuan Lu, 2008, IEEE Electron Device Letters.

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

Shi-Yu Huang, Ya-Chin King, Cheng-Hsiao Lai, 2006 .

An ultra-low dark current CMOS image sensor cell using n/sup +/ ring reset

Ya-Chin King, Hsiu-Yu Cheng, Y. King, 2002 .

Charge-based capacitance measurement for bias-dependent capacitance

Yao-Wen Chang, Ya-Chin King, Chih-Yuan Lu, 2006 .

On-state reliability of amorphous silicon antifuses

Ya-Chin King, P. Yu, E. Hamdy, 1995, Proceedings of International Electron Devices Meeting.

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations

Ya-Chin King, Hsiu-Yu Cheng, Y. King, 2003 .

A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model

Ya-Chin King, Chrong-Jung Lin, Y. King, 2018, Nanoscale Research Letters.

Dc electrical oxide thickness model for quantization of the inversion layer in MOSFETs

Ya-Chin King, Chenming Hu, Y. King, 1998 .

Three-Dimensional $\hbox{4F}^{2}$ ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

Heng-Yuan Lee, Ming-Jinn Tsai, Ya-Chin King, 2011, IEEE Transactions on Electron Devices.

Magnetic Wireless Interlayer Transmission Through Perpendicular MTJ for 3-D IC Applications

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2014, IEEE Transactions on Electron Devices.

High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

Ya-Chin King, Chrong Jung Lin, An-Chi Kang, 2008 .

Influence of Passivation Layers on Characteristics of a-InGaZnO Thin-Film Transistors

Yung-Hui Yeh, Ya-Chin King, Chun-Cheng Cheng, 2011, IEEE Electron Device Letters.

Integrated ambient light sensor in LTPS LCD panel with silicon nanocrystals photosensor

Ya-Chin King, Chrong Jung Lin, Wen-Jen Chiang, 2007 .

Embedded Optical Sensor Using Gate-Body-Tied Thin-Film Transistor on Low-Temperature Poly-Silicon Display Panel

Ya-Chin King, Chrong Jung Lin, Wen-Jen Chiang, 2009 .

A voltage acceleration lifetime model to predict post-cycling LTDR characteristics of split-gate flash memories

Ya-Chin King, J.R. Shih, Ling-Chang Hu, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology

Ya-Chin King, Min-Che Hsieh, Yung-Wen Chin, 2013, IEEE Electron Device Letters.

Increasing VG-type 3D NAND flash cell density by using ultra-thin poly-silicon channels

Tahone Yang, Ya-Chin King, Hang-Ting Lue, 2013, 2013 5th IEEE International Memory Workshop.

New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides

Ya-Chin King, Mong-Song Liang, Cheng-Jye Liu, 2001 .

MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs

Ya-Chin King, Yu-Cheng Chen, Y. King, 2006 .

Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/

Ya-Chin King, Chenming Hu, Tsu-Jae King, 2001 .

A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application

Rich Liu, Ya-Chin King, Hang-Ting Lue, 2007 .

New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications

Ya-Chin King, Kung-Hong Lee, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

TiN Thickness Impact on BTI Performance

Ya-Chin King, Chien Liang Chen, 2011, IEEE Electron Device Letters.

Punchthrough transient voltage suppressor for EOS/ESD protection of low-voltage IC's

Ya-Chin King, Chenming Hu, Bin Yu, 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

Embedded TFT nand-Type Nonvolatile Memory in Panel

Ya-Chin King, Chrong-Jung Lin, Hung-Tse Chen, 2007, IEEE Electron Device Letters.

Threshold voltage uniformity enhancement for low-temperature polysilicon thin-film transistors using tilt alignment technique

Ya-Chin King, Yu-Cheng Chen, Y. King, 2006 .

A novel high-density embedded AND-type split gate flash memory

Ya-Chin King, Chrong Jung Lin, Chiu-Wang Lien, 2014 .

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction

Ya-Chin King, Liang-Wei Lai, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Reliability evaluation and comparison of Class-E and Class-A power amplifiers with 0.18 /spl mu/m CMOS technology

Ya-Chin King, Wei-Cheng Lin, Long-Jei Du, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process

Ya-Chin King, Chrong Jung Lin, Min-Che Hsieh, 2014, 2014 IEEE International Electron Devices Meeting.

High Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology

Peng-Chun Liou, Yu-Lun Chueh, Jonathan Chang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

AC Charge Centroid Model For Quantization Of Inversion Layer In N-MOSFET

Ya-Chin King, Chenming Hu, Wen-Chin Lee, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

Thin dielectric technology and memory devices

Ya-Chin King, 1999 .

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide

Ya-Chin King, Chenming Hu, Tsu-Jae King, 1999 .