K. Shin

A 330 MHz 4-way superscalar microprocessor

H. Sathianathan, S. Shah, D. Greenhill, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

64 kB sum-addressed-memory cache with 1.6 ns cycle and 2.6 ns latency

R. Heald, M. Khan, G. Lauterbach, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).