Tripti Sharma

发表

High speed, low power 8t full adder cell with 45% improvement in threshold loss problem

Tripti Sharma, B. P. Singh, K. G. Sharma, 2010, ICN 2010.

Fuzzy Based Ant Colony Optimization Approach for Wireless Sensor Network

Brijesh Kumar Chaurasia, Tripti Sharma, G. S. Tomar, 2015, Wirel. Pers. Commun..

SET D-flip flop design for portable applications

Tripti Sharma, K. G. Sharma, Neha Arora, 2011, India International Conference on Power Electronics 2010 (IICPE2010).

PMOS based 1-Bit Full Adder Cell

Tripti Sharma, B. P. Singh, K. G. Sharma, 2012 .

Low Power 1-Bit 9T Full Adder Cell using XNOR Logic

Tripti Sharma, B. P. Singh, Shiwani Singh, 2012 .

Design and Analysis of 8T Full Adder Cell Using Double Gate MOSFET

Tripti Sharma, K. G. Sharma, 2014 .

Interconnect Repeater Design for Portable Applications

Tripti Sharma, Neha Arora, B. P. Singh, 2010 .

Optimized battery threshold for better network connectivity

Tripti Sharma, Anshu Chaturvedi, D. N. Goswami, 2014, Int. J. Syst. Assur. Eng. Manag..

Full Adder Circuits using Static Cmos Logic Style: A Review

Tripti Sharma, Sugandha Chauhan, 2017 .

Rail-to-rail two stage CMOS operational amplifier: A comparative analysis

Tripti Sharma, Anil Sharma, Bobbinpreet Kaur, 2018, 2018 2nd International Conference on Inventive Systems and Control (ICISC).

Energy efficient interface circuits between adiabatic and standard CMOS logic at 90 nm technology

Tripti Sharma, Neha Arora, B. P. Singh, 2010, ICN 2010.

Design and analysis of low power 1-bit full adder cell

Tripti Sharma, K. G. Sharma, Deepa Sinha, 2011, 2011 3rd International Conference on Electronics Computer Technology.

Ultra Low Power 1-Bit Full Adder

Tripti Sharma, B. P. Singh, K. G. Sharma, 2011 .

Adiabatic and standard CMOS interfaces at 90 nm technology

Tripti Sharma, B. P. Singh, Neha Arora, 2010 .

Array Multiplier using pMOS based 3T XOR Cell

Tripti Sharma, B. P. Singh, Shiwani Singh, 2012 .

A Novel Latch design for Low Power Applications

Tripti Sharma, B. P. Singh, K. G. Sharma, 2012 .

High Performance and Function Design on the Transistor Level

Tripti Sharma, K. G. Sharma, 2013 .

High Performance VLSI Design Using Body Biasing in Domino Logic Circuits

Tripti Sharma, K. G. Sharma, B. P. Singh, 2011 .

Intercluster Ant Colony Optimization Algorithm for Wireless Sensor Network in Dense Environment

Brijesh Kumar Chaurasia, Tripti Sharma, Won-Hyung Lee, 2014, Int. J. Distributed Sens. Networks.

New Efficient 2T and Gate Design

Tripti Sharma, 2011 .

New Approach to Low Power Full Adder Cell

Tripti Sharma, K. G. Sharma, Shiwani Singh, 2012 .

A novel CMOS 1-bit 8T full adder cell

Tripti Sharma, B. P. Singh, K. G. Sharma, 2010 .

Single Edge Triggered Static D Flip-Flops: Performance Comparison

Tripti Sharma, Kanchan Sharma, K. G. Sharma, 2015 .

Performance enhancement of a hybrid 1-bit full adder circuit

Tripti Sharma, Sugandha Chauhan, T. Sharma, 2016, 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES).

Efficient design for transistor level and function

Tripti Sharma, K. G. Sharma, B. P. Singh, 2011, 2011 3rd International Conference on Electronics Computer Technology.

High Performance Latch Design for Portable Application

Tripti Sharma, K. G. Sharma, B. P. Singh, 2012 .

Area Efficient Level Sensitive Flip-Flops – A Performance Comparison

Tripti Sharma, K. G. Sharma, Tripti Dua, 2014 .

Design and performance analysis of phase frequency detector for high speed application

Tripti Sharma, Bobbinpreet Kaur, Archna Dhiman, 2018, 2018 2nd International Conference on Inventive Systems and Control (ICISC).

Novel Adiabatic‐CMOS Interfaces

Tripti Sharma, K. G. Sharma, Neha Arora, 2010 .

Low Power 3T XOR Cell using IDDG MOSFET

Tripti Sharma, K. G. Sharma, Ruchika Ruchika, 2014 .

A Genetic Algorithm based Feature Optimization method for Citrus HLB Disease Detection using Machine Learning

Tripti Sharma, Bobbinpreet Kaur, Ayush Dogra, 2020, 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT).

High performance full adder cell: A comparative analysis

Tripti Sharma, B.P. Singh, K.G. Sharma, 2010, 2010 IEEE Students Technology Symposium (TechSym).

9T Full Adder Design in Subthreshold Region

Tripti Sharma, K. G. Sharma, B. P. Singh, 2012, VLSI Design.

New Efficient Design for XOR Function on the Transistor Level

Tripti Sharma, Neha Arora, B. P. Singh, 2010 .

Low Power Magnitude Comparator Circuit Design

Tripti Sharma, K. G. Sharma, Vijaya Shekhawat, 2014 .

NEW DESIGN OF LOW POWER 3T XOR CELL

Tripti Sharma, B. P. Singh, Shiwani Singh, 2012 .

High Performance Domino Logic Circuits in Low Power VLSI Design

Tripti Sharma, Suman Nehra, K. G. Sharma, 2012 .

A New Technique For Designing Low Power 2-Bit Magnitude Comparator

Tripti Sharma, Vijaya Shekhawat, K. G. Sharma, 2014 .

Ultra low power and high performance full adder design

Tripti Sharma, 2012 .

Performance Analysis on Low-Power, Low-Offset, High-Speed Comparator for High-Speed ADCA Review

Tripti Sharma, Simran Somal, Krishan Mehra, 2021 .

High Speed Array Multipliers Based on 1-Bit Full Adders

Tripti Sharma, K. G. Sharma, B. P. Singh, 2010 .