Kun-Han Tsai

发表

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

Akshay Gupta, Wu-Tung Cheng, Nandu Tendolkar, 2006, 2006 IEEE International Test Conference.

Delay-fault diagnosis using timing information

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

Chen Wang, Kun-Han Tsai, Xijiang Lin, 2006, 2006 15th Asian Test Symposium.

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2014, 2014 19th IEEE European Test Symposium (ETS).

Speed-Path Debug Using At-Speed Scan Test Patterns

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2009, 2009 14th IEEE European Test Symposium.

Monitoring the delay of long interconnects via distributed TDC

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2015, 2015 IEEE International Test Conference (ITC).

Embedded deterministic test for low cost manufacturing test

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2002, Proceedings. International Test Conference.

Compactor independent direct diagnosis

Janusz Rajski, Wu-Tung Cheng, Kun-Han Tsai, 2004, 13th Asian Test Symposium.

Compression mode diagnosis enables high volume monitoring diagnosis flow

Wu-Tung Cheng, Peter Muhmenthaler, Kun-Han Tsai, 2005, IEEE International Conference on Test, 2005..

Improving the Resolution of Single-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhancing Transition Fault Model for Delay Defect Diagnosis

Ruifeng Guo, Kun-Han Tsai, Wu-Tung Cheng, 2008, 2008 17th Asian Test Symposium.

Clock-domain-aware test for improving pattern compression

Janusz Rajski, Kun-Han Tsai, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Small delay testing for TSVs in 3-D ICs

Shi-Yu Huang, Wu-Tung Cheng, Ding-Ming Kwai, 2012, DAC Design Automation Conference 2012.

Test coverage debugging for designs with timing exception paths

Kun-Han Tsai, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Multicycle-aware At-speed Test Methodology

Kun-Han Tsai, Xijiang Lin, 2013, 2013 22nd Asian Test Symposium.

Scan-Based Speed-Path Debug for a Microprocessor

Jing Wang, Jing Zeng, Wu-Tung Cheng, 2012, IEEE Design & Test of Computers.

Realizing high test quality goals with smart test resource usage

Janusz Rajski, Xinli Gu, Kun-Han Tsai, 2004 .

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2016, IEEE Design & Test.

A Robust Automated Scan Pattern Mismatch Debugger

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2008, 2008 17th Asian Test Symposium.

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, ISQED 2008.

Design rule check on the clock gating logic for testability and beyond

Kun-Han Tsai, Shuo Sheng, 2013, 2013 IEEE International Test Conference (ITC).

A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems

Chih-Peng Li, Kun-Han Tsai, Sen-Hung Wang, 2010, 2010 IEEE International Conference on Communications.

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

Shi-Yu Huang, Wu-Tung Cheng, Li-Ren Huang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Diagnostic test generation for small delay defect diagnosis

Ruifeng Guo, Kun-Han Tsai, Wu-Tung Cheng, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

At-Speed Scan Test Method for the Timing Optimization and Calibration

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2009, 2009 Asian Test Symposium.

Enhanced testing of clock faults

Kun-Han Tsai, Teresa L. McLaurin, Rich Slobodnik, 2007, 2007 IEEE International Test Conference.

Oscillation-Based Prebond TSV Test

Shi-Yu Huang, Wu-Tung Cheng, Li-Ren Huang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Impact of multiple-detect test patterns on product quality

Janusz Rajski, Kun-Han Tsai, Nagesh Tamarapalli, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

STARBIST: scan autocorrelated random pattern generation

Malgorzata Marek-Sadowska, Janusz Rajski, Sybille Hellebrand, 1997, DAC.

A wide-range clock signal generation scheme for speed grading of a logic core

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2016, 2016 International Conference on High Performance Computing & Simulation (HPCS).

Feedback-bus oscillation ring: A general architecture for delay characterization and test of interconnects

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Improved handling of false and multicycle paths in ATPG

Dhiraj Goswami, Kun-Han Tsai, Bruce Swanson, 2006, 24th IEEE VLSI Test Symposium.

Analysis and methodology for multiple-fault diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Circuit and Methodology for Testing Small Delay Faults in the Clock Network

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs

Shi-Yu Huang, Wu-Tung Cheng, Li-Ren Huang, 2013, 2013 IEEE International Test Conference (ITC).

Programmable Leakage Test and Binning for TSVs

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2012, 2012 IEEE 21st Asian Test Symposium.

Scan-Encoded Test Pattern Generation for BIST

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 1997, ITC.

Built-in constraint resolution

Grady Giles, Kun-Han Tsai, Daniela Toneva, 2005, IEEE International Conference on Test, 2005..

Testing of small delay faults in a clock network

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2016, 2016 21th IEEE European Test Symposium (ETS).

Test Generation in the Presence of Timing Exceptions and Constraints

Dhiraj Goswami, Janusz Rajski, Kun-Han Tsai, 2007, 2007 44th ACM/IEEE Design Automation Conference.

X-Sources Analysis for Improving the Test Quality

Kun-Han Tsai, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control

Shi-Yu Huang, Wu-Tung Cheng, Li-Ren Huang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Realizing high test quality goals with smart test resource usage

Janusz Rajski, Xinli Gu, Jan Arild Tofte, 2004, 2004 International Conferce on Test.

GPGPU-Based ATPG System: Myth or Reality?

Kun-Han Tsai, Liyang Lai, Huawei Li, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Online slack-time binning for IO-registered die-to-die interconnects

Shyue-Kung Lu, Shi-Yu Huang, Ting-Chi Wang, 2016, 2016 IEEE International Test Conference (ITC).

A scalable quantitative measure of IR-drop effects for scan pattern generation

Wu-Tung Cheng, Jiun-Lang Huang, Kun-Han Tsai, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Test Coverage Analysis for Designs with Timing Exceptions

Kun-Han Tsai, Srinivasan Gopalakrishnan, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Mid-bond Interposer Wire Test

Shi-Yu Huang, Wu-Tung Cheng, Li-Ren Huang, 2013, 2013 22nd Asian Test Symposium.

Improved weight assignment for logic switching activity during at-speed test pattern generation

Wu-Tung Cheng, Jiun-Lang Huang, Kun-Han Tsai, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs

Kun-Han Tsai, Kun-Han Tsai, 2014, 2014 IEEE 23rd Asian Test Symposium.

Diagnosis of hold time defects

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

A unified method for parametric fault characterization of post-bond TSVs

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2012, 2012 IEEE International Test Conference.

Multiple fault diagnosis using n-detection tests

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2003, Proceedings 21st International Conference on Computer Design.

Improve speed path identification with suspect path expressions

Wu-Tung Cheng, Jiun-Lang Huang, Manish Sharma, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test cycle power optimization for scan-based designs

Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, 2010, 2010 IEEE International Test Conference.

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2014, 2014 IEEE 23rd Asian Test Symposium.

Delay fault diagnosis for nonrobust test

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

An efficient and effective methodology on the multiple fault diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, 2006 IEEE International Test Conference.

A test-application-count based learning technique for test time reduction

Wu-Tung Cheng, Jiun-Lang Huang, Kun-Han Tsai, 2015, VLSI Design, Automation and Test(VLSI-DAT).

At-speed BIST for interposer wires supporting on-the-spot diagnosis

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

At-Speed Testing with Timing Exceptions and Constraints-Case Studies

Kun-Han Tsai, M. Kassab, J. Rajski, 2006, 2006 15th Asian Test Symposium.

Delay-fault diagnosis using timing information

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Star test: the theory and its applications

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

Shi-Yu Huang, Wu-Tung Cheng, Ding-Ming Kwai, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks

Yu Huang, Shi-Yu Huang, Wu-Tung Cheng, 2019, ASP-DAC.

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC

Shi-Yu Huang, Wu-Tung Cheng, Kun-Han Tsai, 2016, IEEE Design & Test.

Timing Critical Path Validation for Intel ATOM Cores Using Structural Test

Kun-Han Tsai, Xijiang Lin, Khen Wee, 2021, 2021 IEEE 39th VLSI Test Symposium (VTS).