S. B. Park

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth

Hoi-Jun Yoo, Se-Joong Lee, Ramchan Woo, 2002, IEEE J. Solid State Circuits.

Hidden double data transfer scheme for MDL design

Hoi-Jun Yoo, S. B. Park, H. Yoo, 2001 .

Design and implementation of a new four-quadrant MOS analog multiplier

S. B. Park, C. W. Kim, C. Kim, 1992 .

Delay-time modelling and critical-path verification for digital designs

K. H. Kim, S. B. Park, S. B. Park, 1991, Comput. Aided Des..