L. Su

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

D. Kramer, S. Geissler, N. Rohrer, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology

P. Roper, D. Edelstein, J. Heidenreich, 1997, International Electron Devices Meeting. IEDM Technical Digest.

RF perspective of sub-tenth-micron CMOS

C. Wann, Y. Taur, L. Su, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

FP 15.6: A 480MHz RISC Microprocessor in a 0.12pm Le, CMOS Technology with Copper Interconnects

Robert M. Houle, C. Akrout, M. Canada, 1998 .

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates

S. Crowder, L. Su, E. Crabbe, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Sub-60 nm physical gate length SOI CMOS

J. Sleight, E. Maciejewski, E. Nowak, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

S. Narasimha, J. Adkisson, E. Maciejewski, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A high-performance 0.08 /spl mu/m CMOS

E. Nowak, A. Ray, P. Agnello, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.