Tien-Hao Tang

发表

Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

Chun Chiang, Ping-Chen Chang, Pei-Shan Tseng, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Ming-Dou Ker, Chun Chiang, Ping-Chen Chang, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

A novel high level ESD FDNSCR with drain side engineering in PMIC application

Tien-Hao Tang, Kuan-Cheng Su, Yi-Ning He, 2015, 2015 IEEE International Reliability Physics Symposium.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, IPFA 2010.

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Tien-Hao Tang, Kuan-Cheng Su, Yu-Chun Chen, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2009, 2009 IEEE International Conference on IC Design and Technology.

Latch-up free ESD protection design with SCR structure in advanced CMOS technology

Tien-Hao Tang, Kuan-Cheng Su, Chang-Tzu Wang, 2011, 2011 International Reliability Physics Symposium.

Low-leakage diode string designs using triple-well technologies for RF-ESD applications

Tung-Yang Chen, Tien-Hao Tang, Chiu-Hsiang Chou, 2003 .

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

Tien-Hao Tang, Kuan-Cheng Su, Tai-Hsiang Lai, 2011, 2011 International Reliability Physics Symposium.

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

Tien-Hao Tang, Kuan-Cheng Su, Chang-Tzu Wang, 2011, 2011 International Reliability Physics Symposium.

Lower trigger voltage design for ESD protection device applied in PMIC application

Tien-Hao Tang, Kuan-Cheng Su, Yi-Ning He, 2014, 2014 IEEE International Reliability Physics Symposium.

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2008, 2008 IEEE International Reliability Physics Symposium.

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

Tung-Yang Chen, Tien-Hao Tang, Jenkon Chen, 2003 .