Kuan-Cheng Su

发表

Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

Chun Chiang, Ping-Chen Chang, Pei-Shan Tseng, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Ming-Dou Ker, Chun Chiang, Ping-Chen Chang, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

A novel high level ESD FDNSCR with drain side engineering in PMIC application

Tien-Hao Tang, Kuan-Cheng Su, Yi-Ning He, 2015, 2015 IEEE International Reliability Physics Symposium.

Comprehensive hot carrier mechanism investigation of 40V LDNMOS transistor

Kuan-Cheng Su, Yi-Chun Wang, Yi-Pin Chen, 2007, 2007 IEEE International Integrated Reliability Workshop Final Report.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, IPFA 2010.

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Tien-Hao Tang, Kuan-Cheng Su, Yu-Chun Chen, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2009, 2009 IEEE International Conference on IC Design and Technology.

Latch-up free ESD protection design with SCR structure in advanced CMOS technology

Tien-Hao Tang, Kuan-Cheng Su, Chang-Tzu Wang, 2011, 2011 International Reliability Physics Symposium.

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

Tien-Hao Tang, Kuan-Cheng Su, Tai-Hsiang Lai, 2011, 2011 International Reliability Physics Symposium.

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

Tien-Hao Tang, Kuan-Cheng Su, Chang-Tzu Wang, 2011, 2011 International Reliability Physics Symposium.

Novel input ESD protection circuit with substrate-triggering technique in a 0.25-/spl mu/m shallow-trench-isolation CMOS technology

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Ultra-Fast Negative Bias Temperature Instability Monitoring and End-of-Life Projection

Kuan-Cheng Su, Chi-Shiun Wang, Wen-Chun Chang, 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

Lower trigger voltage design for ESD protection device applied in PMIC application

Tien-Hao Tang, Kuan-Cheng Su, Yi-Ning He, 2014, 2014 IEEE International Reliability Physics Symposium.

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2008, 2008 IEEE International Reliability Physics Symposium.

Self-Heating p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors for Reliability Monitoring of Negative-Bias Temperature Instability

Kuan-Cheng Su, Ting-Kuo Kang, Chi-Shiun Wang, 2007 .