Hon Nin Cheung

VLSI architecture for significance map coding of embedded zerotree wavelet coefficients

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Robust image compression using the depth-first search on the wavelet zerotree

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 1999, ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359).

Smart pixel VLSI architecture for embedded zerotree wavelet coding

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 1999, ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359).

Circuit allocation in subtransmission switching substations using best-first search strategy

Kit Po Wong, Hon Nin Cheung, 1988 .

EZW algorithm using depth-first representation of the wavelet zerotree

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 1999, ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359).

An efficient approach to constrained via minimization for two-layer VLSI routing

Kamran Eshraghian, Hon Nin Cheung, Maolin Tang, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Parallel architecture for the implementation of the embedded zerotree wavelet algorithm

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 2000, Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512).

Properties of shunting inhibitory cellular neural networks for colour image enhancement

Abdesselam Bouzerdoum, Hon Nin Cheung, W. Newland, 1999, ICONIP'99. ANZIIS'99 & ANNES'99 & ACNN'99. 6th International Conference on Neural Information Processing. Proceedings (Cat. No.99EX378).

VLSI decoder architecture for embedded zerotree wavelet algorithm

Li-Minn Ang, Hon Nin Cheung, K. Eshraghian, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Counterpropagation network and time-frequency shift-tolerant preprocessing for phoneme recognition

Li-Minn Ang, Hon Nin Cheung, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A genetic algorithm for constrained via minimization

Kamran Eshraghian, Hon Nin Cheung, Maolin Tang, 1999, ICONIP'99. ANZIIS'99 & ANNES'99 & ACNN'99. 6th International Conference on Neural Information Processing. Proceedings (Cat. No.99EX378).

Hardware implementation of the depth first search bit stream SPIHT system

Li-Minn Ang, Hon Nin Cheung, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

VLSI architecture for very high resolution scalable video coding using the virtual zerotree

Li-Minn Ang, Kamran Eshraghian, Hon Nin Cheung, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).