Tsukasa Oishi

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes

Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, 2013, IEICE Trans. Electron..

A new array architecture for parallel testing in VLSI memories

Masaki Tsukude, Kazutami Arimoto, Kazuyasu Fujishima, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

A low power NoC router using the marching memory through type

Hideharu Amano, Masashi Watanabe, Tadao Nakamura, 2014, 2014 IEEE COOL Chips XVII.

A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration

Toshio Kumamoto, Yasunobu Nakase, Yasuhiro Ido, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU

Shinji Kawai, Shigehiro Kuge, Toshihiro Abe, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Design of a low power NoC router using Marching Memory Through type

Hideharu Amano, Masashi Watanabe, Tadao Nakamura, 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers

Wei Zhang, Wei Kong, Yasunobu Nakase, 2011, IEEE Asian Solid-State Circuits Conference 2011.

0.5 V Start-Up 87% Efficiency 0.75 mm² On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

Toshio Kumamoto, Yasunobu Nakase, Yasuhiro Ido, 2013, IEEE Journal of Solid-State Circuits.