Chang Gyu Hwang

A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Seung-Moon Yoo, Jin Man Han, Soo-In Cho, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SADD) process for 0.15 /spl mu/m stand-alone and embedded DRAMs

Kinam Kim, Jong-Ho Lee, Won Seok Lee, 1999 .

A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

Hongil Yoon, Kinam Kim, Chang Hyun Choi, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).