S. Tomari

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

Y. Amamiya, Z. Yamazaki, R. Ohhira, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication

M. Fukaishi, M. Kurisu, K. Nakamura, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

Y. Amamiya, Z. Yamazaki, H. Ikeda, 2009, IEEE Journal of Solid-State Circuits.