J. R. Armstrong

Computer Logic, Testing and Verification. By Paul Roth

J. R. Armstrong, 1983 .

An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow

J. G. Tront, J. R. Armstrong, K. W. Li, 1984, IEEE Transactions on Nuclear Science.

Efficiency ratings for VHDL behavioral models

J. A. Wicks, J. R. Armstrong, 1998, Proceedings IEEE Southeastcon '98 'Engineering for a New Era'.

An automatic test bench generation system

S. Kapoor, J. R. Armstrong, S. R. Rao, 1994, Proceedings of VHDL International Users Forum.

Hierarchical test generation for VHDL behavioral models

J. R. Armstrong, S. R. Rao, Bi-Yu Pan, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

2 Model and Synthesis Directed Task Assignment for Systems On A Chip

J. R. Armstrong, J. Armstrong, Pradeep Adipathi, 2002 .