Tapan J. Chakraborty

发表

Delay fault models and test generation for random logic sequential circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

A New Language Approach for IJTAG

Bradford G. Van Treuren, Tapan J. Chakraborty, Michele Portolan, 2008, 2008 IEEE International Test Conference.

Built in self test: a complete test solution for telecommunication systems

Nilanjan Mukherjee, Ramesh Karri, Tapan J. Chakraborty, 1999, IEEE Commun. Mag..

Delay independent initialization of sequential circuits

Vishwani D. Agrawal, Tapan J. Chakraborty, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

Functional Fmax test-time reduction using novel DFTs for circuit initialization

Mark Mohammad Tehranipoor, Ujjwal Guin, Tapan J. Chakraborty, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

A practical approach to comprehensive system test & debug using boundary scan based test architecture

Bradford G. Van Treuren, Tapan J. Chakraborty, Chen-Huan Chiang, 2007, 2007 IEEE International Test Conference.

Simulation of at-speed tests for stuck-at faults

Vishwani D. Agrawal, Tapan J. Chakraborty, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Design for Testability for Path Delay Faults in Sequential Circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 1993, 30th ACM/IEEE Design Automation Conference.

A BIST scheme for the detection of path-delay faults

Nilanjan Mukherjee, Sudipta Bhawmik, Tapan J. Chakraborty, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

On behavior fault modeling for digital designs

Sumit Ghosh, Tapan J. Chakraborty, Sumit Ghosh, 1991, J. Electron. Test..

High-performance circuit testing with slow-speed testers

Vishwani D. Agrawal, Tapan J. Chakraborty, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Design for high-speed testability of stuck-at faults

Vishwani D. Agrawal, Tapan J. Chakraborty, 1996, Proceedings of 9th International Conference on VLSI Design.

Path delay fault simulation of sequential circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 2000, IEEE Trans. Very Large Scale Integr. Syst..

A Common Language Framework for Next-Generation Embedded Testing

Bradford G. Van Treuren, Tapan J. Chakraborty, Michele Portolan, 2010, IEEE Design & Test of Computers.

Enhanced controllability for IDDQ test sets using partial scan

Chih-Jen Lin, Sudipta Bhawmik, Tapan J. Chakraborty, 1991, 28th ACM/IEEE Design Automation Conference.

Automatic test generation for digital electronic circuits

Kwang-Ting Cheng, Scott Davidson, Tapan J. Chakraborty, 1994, AT&T Technical Journal.

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Robust testing for stuck-at faults

Vishwani D. Agrawal, Tapan J. Chakraborty, 1995, Proceedings of the 8th International Conference on VLSI Design.

Partial scan testing with single clock control

Vishwani D. Agrawal, Tapan J. Chakraborty, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

On behavior fault modeling for combinational digital designs

Sumit Ghosh, Tapan J. Chakraborty, Sumit Ghosh, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Effective path selection for delay fault testing of sequential circuits

Vishwani D. Agrawal, Tapan J. Chakraborty, 1997, Proceedings International Test Conference 1997.

Gentest: an automatic test-generation system for sequential circuits

Wu-Tung Cheng, Tapan J. Chakraborty, T. Chakraborty, 1989, Computer.

On variable clock methods for path delay testing of sequential circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improving path delay testability of sequential circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 2000, IEEE Trans. Very Large Scale Integr. Syst..

FPGA Prototyping of a Scan Based System-On-Chip Design

Michael Higgins, Tapan J. Chakraborty, Brendan Mullane, 2007, ReCoSoC.