Jih-Jeen Chen

Peak-power reduction for multiple-scan circuits during test application

Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Test pattern generation and clock disabling for simultaneous test time and power reduction

Kuen-Jong Lee, Chia-Kai Yang, Jih-Jeen Chen, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Using a single input to support multiple scan chains

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang, 1998, ICCAD.

Broadcasting test patterns to multiple circuits

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Using a single input to support multiple scan chains

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang, 1998, ICCAD '98.

Reducing test application time and power dissipation for scan-based testing via multiple clock disabling

Kuen-Jong Lee, Jih-Jeen Chen, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..