G. Van der Plas

发表

Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery

J. Ryckaert, A. Gupta, A. Jourdain, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies

P. Wambacq, A. Mercha, G. Van der Plas, 2013, 2013 IEEE International Electron Devices Meeting.

A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS

J. Ryckaert, G. Van der Plas, V. De Heyn, 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

Behavioral model for D/A converters as VSI virtual components

G. Van der Plas, W. Sansen, M. Steyaert, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology

E. Beyne, J. Ryckaert, G. Van der Plas, 2014, 2014 IEEE 18th Workshop on Signal and Power Integrity (SPI).

A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL

W. Dehaene, G. Gielen, G. Van der Plas, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

IC-Package Interaction

M. Gonzalez, E. Beyne, G. Van der Plas, 2013, 2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

Fast and Accurate Modelling of Large TSV Arrays in 3D-ICs Using a 3D Circuit Model Validated Against Full-Wave FEM Simulations and RF Measurements

E. Beyne, G. Van der Plas, M. Rack, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Statistical behavioral modeling for A/D-converters

G. Van der Plas, W. Sansen, G. Gielen, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

A 12 bit 200 MHz low glitch CMOS D/A converter

G. Van der Plas, W. Sansen, M. Steyaert, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Performance degradation of an LC-tank VCO by impact of digital switching noise

P. Wambacq, G. Van der Plas, S. Donnay, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

Analysis of substrate noise propagation in a lightly doped substrate [mixed-signal ICs]

P. Wambacq, G. Van der Plas, S. Donnay, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

EsteMate: a tool for automated power and area estimation in analog top-down design and synthesis

G. Van der Plas, W. Sansen, G. Gielen, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

H. De Man, G. Van der Plas, M. Badaroglu, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

Mondriaan: a tool for automated layout synthesis of array-type analog blocks

G. Van der Plas, W. Sansen, G. Gielen, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Study of the different coupling mechanisms between a 4 GHz PPA and a 5–7 GHz LC-VCO

G. Van der Plas, Y. Rolain, L. De Locht, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

Active-lite interposer for 2.5 & 3D integration

E. Beyne, G. Van der Plas, G. Hellings, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

RF characterization and modeling of through-silicon vias

E. Beyne, J. Ryckaert, G. Van der Plas, 2013, 2013 Eurpoean Microelectronics Packaging Conference (EMPC).

Study of 3D process impact on advanced CMOS devices

E. Beyne, Anne Jourdain, G. Van der Plas, 2013, 2013 Eurpoean Microelectronics Packaging Conference (EMPC).

On-chip circuit for massively parallel BTI characterization

G. Groeseneken, B. Kaczer, G. Van der Plas, 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Substrate Noise Isolation Experiments in a 0.18 μm 1P6M Triple-well CMOS process on a Lightly Doped Substrate

G. Van der Plas, C. Soens, M. Rizzi, 2007, 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007.

A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass ΣΔ ADC in 90nm CMOS

J. Ryckaert, G. Van der Plas, L. Van der Perre, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

Reliability concerns in copper TSV's: Methods and results

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

E. Beyne, G. Van der Plas, I. De Wolf, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

E. Beyne, G. Van der Plas, V. Cherman, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

E. Beyne, G. Van der Plas, V. Cherman, 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

High efficiency direct liquid jet impingement cooling of high power devices using a 3D-shaped polymer cooler

E. Beyne, G. Van der Plas, I. De Wolf, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal ICs on a lightly-doped substrate

G. Van der Plas, M. Badaroglu, S. Donnay, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

FET arrays as CPI sensors for 3D stacking and packaging characterization

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

A. Mercha, G. Van der Plas, D. Verkest, 2013, 2013 Symposium on VLSI Circuits.

On the P+ guard ring sizing strategy to shield against substrate noise

G. Van der Plas, Y. Rolain, S. Bronckers, 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS

G. Van der Plas, M. Kuijk, B. Verbruggen, 2008, 2008 IEEE Symposium on VLSI Circuits.

Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

E. Beyne, J. De Vos, G. Van der Plas, 2016, 2016 IEEE MTT-S International Microwave Symposium (IMS).

Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Fine grain thermal modeling of 3D stacked structures

G. Van der Plas, E. Cheng, A. Srinivasan, 2009, 2009 15th International Workshop on Thermal Investigations of ICs and Systems.