Dinesh Somasekhar

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2002 .

On The Design of Adiabatic SRAMs

Kaushik Roy, Yibin Ye, Dinesh Somasekhar, 1996 .

Multiple word line access and access device

Shih-Lien Lu, Dinesh Somasekhar, Vivek De, 2002 .

Leakage grading of inputs to CMOS logic

Kaushik Roy, Dinesh Somasekhar, Mark C. Johnson, 1998 .

Noise suppression for DRAM architectures open bit line

Shih-Lien Lu, Dinesh Somasekhar, Vivek De, 2001 .

The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1997 .

An energy recovery static RAM memory core

Kaushik Roy, Yibin Ye, Dinesh Somasekhar, 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

Noise reduction system for a dynamic random access memory device

Shih-Lien Lu, Dinesh Somasekhar, Vivek De, 2001 .

Session details: Power optimizations for cache memory

Renu Mehra, Dinesh Somasekhar, 2004, ISLPED '04.