Ahmed Elkholy

发表

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, 2019, IEEE Journal of Solid-State Circuits.

A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2017, IEEE Journal of Solid-State Circuits.

A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation

Ahmed Elkholy, Pavan Kumar Hanumolu, Ahmed Elmallah, 2019, IEEE Trans. Circuits Syst. II Express Briefs.

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with −106dBc/Hz In-band noise using time amplifier based TDC

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2015, IEEE Journal of Solid-State Circuits.

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2019, IEEE Journal of Solid-State Circuits.

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2017, IEEE J. Solid State Circuits.

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Mostafa Gamal Ahmed, 2020, IEEE Journal of Solid-State Circuits.

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection

Ahmed Elkholy, Pavan Kumar Hanumolu, Karim M. Megawer, 2019, IEEE Journal of Solid-State Circuits.

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

18.5 A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Karim M. Megawer, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Mohamed Elzeftawi, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2017, IEEE Journal of Solid-State Circuits.

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS

Ahmed Elkholy, Tejasvi Anand, Amr Elshazly, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Arabian horse identification based on whale optimised multi-class support vector machine

Ahmed Elkholy, Aboul Ella Hassanien, Ashraf Darwish, 2020, Int. J. Comput. Appl. Technol..

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Guanghua Shu, 2017, IEEE Journal of Solid-State Circuits.

A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Guanghua Shu, 2018, IEEE Journal of Solid-State Circuits.

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2016, IEEE Journal of Solid-State Circuits.

Arabian Horse Identification and Gender Determination System based on Feature Fusion and Gray Wolf Optimization

Ahmed Elkholy, Aboul Ella Hassanien, Ashraf Darwish, 2020 .

A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

Ahmed Elkholy, Pavan Kumar Hanumolu, Ahmed Elmallah, 2018, IEEE Journal of Solid-State Circuits.

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

Ahmed Elkholy, Tejasvi Anand, Amr Elshazly, 2015, IEEE Journal of Solid-State Circuits.

A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer

Ahmed Elkholy, Pavan Kumar Hanumolu, Karim M. Megawer, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2018, IEEE Journal of Solid-State Circuits.

A 15-Gb/s Sub-Baud-Rate Digital CDR

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2019, IEEE Journal of Solid-State Circuits.

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2016, IEEE Journal of Solid-State Circuits.

A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction

Ahmed Elkholy, Pavan Kumar Hanumolu, Karim M. Megawer, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling

Ahmed Elkholy, Pavan Kumar Hanumolu, Romesh Kumar Nandwana, 2021, IEEE Journal of Solid-State Circuits.

Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65 nm CMOS

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2015 .