Pak K. Chan

发表

EMPIRICAL EVALUATION OF MULTILEVEL LOGIC MINIMIZATION TOOLS FOR A FIELD-PROGRAMMABLE GATE ARRAY TECHNOLOGY

Martine D. F. Schlag, Pak K. Chan, Jackson Kong, 1991 .

A low-offset class-AB CMOS operational amplifier

Liter Siek, Pak K. Chan, Hwee C. Tay, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Analysis and design of CMOS Manchester adders with variable carry-skip

Martine D. F. Schlag, Pak K. Chan, 1989, Proceedings of 9th Symposium on Computer Arithmetic.

Routability-driven technology mapping for lookup table-based FPGA's

Martine D. F. Schlag, Pak K. Chan, Jackson Kong, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Parallel placement for field-programmable gate arrays

Martine D. F. Schlag, Pak K. Chan, 2003, FPGA '03.

Bounds on signal delay in RC mesh networks

Martine D. F. Schlag, Pak K. Chan, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On Routability Prediction for Field-Programmable Gate Arrays

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1993, 30th ACM/IEEE Design Automation Conference.

Computing Signal Delay in General RC Networks by Tree/Link Partitioning

Pak K. Chan, Kevin Karplus, 1989, 26th ACM/IEEE Design Automation Conference.

Routability-driven technology mapping for lookup table-based FPGAs

Martine D. F. Schlag, Pak K. Chan, Jackson Kong, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Spectral-Based Multi-Way FPGA Partitioning

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming

Vojin G. Oklobdzija, Martine D. F. Schlag, Pak K. Chan, 1992, IEEE Trans. Computers.

Algorithms for library-specific sizing of combinational logic

Pak K. Chan, 1991, DAC '90.

A note on designing two-level carry-skip adders

Martine D. F. Schlag, Pak K. Chan, 1991 .

Hybrid spectral/iterative partitioning

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1996, Proceedings of International Conference on Computer Aided Design.

Comments on 'Asymptotic waveform evaluation for timing analysis'

Pak K. Chan, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

New parallelization and convergence results for NC: a negotiation-based FPGA router

Martine D. F. Schlag, Pak K. Chan, P. K. Chan, 2000, FPGA '00.

XS - XILINX 2000/3000 FPGA SIMULATOR

Martine D. F. Schlag, Pak K. Chan, Jackson Kong, 1991 .

Spectral K-way ratio-cut partitioning and clustering

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip

Martine D. F. Schlag, Pak K. Chan, 1990, IEEE Trans. Computers.

Spectral K-Way Ratio-Cut Partitioning and Clustering

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1993, 30th ACM/IEEE Design Automation Conference.

Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology

Martine D. F. Schlag, Pak K. Chan, Jackson Kong, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Delay optimization of carry-skip adders and block carry-lookahead adders

Vojin G. Oklobdzija, Martine D. F. Schlag, Pak K. Chan, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

Computing signal delay in general RC networks by tree/link partitioning

Pak K. Chan, Kevin Karplus, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Reducing compilation time of Zhong's FPGA-based SAT solver

J. Xu, M. Zhu, X. Wang, 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

A FIELD-PROGRAMMABLE PROTOTYPING BOARD: XC4000 BORG USER''S GUIDE

Pak K. Chan, 1994 .

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1996, Proceedings of International Conference on Computer Aided Design.

Acceleration of an FPGA router

Martine D. F. Schlag, Pak K. Chan, 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

Spectral-based multiway FPGA partitioning

Martine D. F. Schlag, Pak K. Chan, Jason Y. Zien, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

BORG: A RECONFIGURABLE PROTOTYPING BOARD USING FIELD-PROGRAMMABLE GATE ARRAYS

Martine D. F. Schlag, Pak K. Chan, Marcelo Martin, 1991 .

Distributed-memory parallel routing for field-programmable gatearrays

Carl Ebeling, Martine D. F. Schlag, Pak K. Chan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hybrid spectral/iterative partitioning

Martine D. F. Schlag, Pak K. Chan, Jason Yeong Zien, 1997, ICCAD 1997.