Ewout Martens

发表

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter

André Bourdoux, Jan Craninckx, Geert Van der Plas, 2012, IEEE Journal of Solid-State Circuits.

Top-Down Heterogeneous Optimization

Georges Gielen, Ewout Martens, 2008 .

High-Level Modeling of Continuous-Time Delta-Sigma A/D Converters

Georges Gielen, Ewout Martens, 2004, DAC 2004.

A model of computation for Continuous-Time Delta-Sigma Modulators

Georges Gielen, Ewout Martens, 2003 .

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators

Georges G. E. Gielen, Ewout Martens, Kenneth Francken, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Journal of Solid-State Circuits.

3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Foundations of Design Flows for Analog and Mixed-Signal Systems

Georges Gielen, Ewout Martens, 2008 .

16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation

Rui P. Martins, Chi-Hang Chan, Jan Craninckx, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Time-Domain Generic Behavioral Models

Georges Gielen, Ewout Martens, G. Gielen, 2008 .

Phase-frequency transfer model of analogue and mixed-signal front-end architectures for system-level design

Georges Gielen, Ewout Martens, 2005 .

A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with −41.3 DB EVM at 1024 OAM in 28NM CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2018, 2018 IEEE Symposium on VLSI Circuits.

A behavioral simulation tool for continuous-time delta-sigma modulators

Georges Gielen, K. Francken, M. Vogels, 2002, ICCAD 2002.

Symbolic Analysis of Front-End Architectures Using Polyphase Harmonic Transfer Matrices

Georges Gielen, Ewout Martens, 2004 .

A behavioral simulation tool for continuous-time /spl Delta//spl Sigma/ modulators

Georges G. E. Gielen, Ewout Martens, Kenneth Francken, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Analog and Mixed-Signal Design Strategies

Georges Gielen, Ewout Martens, 2008 .

DAISY-CT: a high-level simulation tool for continuous-time /spl Delta//spl Sigma/ modulators

K. Francken, M. Vogels, Ewout Martens, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers

Georges G. E. Gielen, Ewout Martens, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion

Ewout Martens, 2018 .

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE Journal of Solid-State Circuits.

Frequency-Domain Generic Behavioral Models

Georges Gielen, Ewout Martens, 2008 .

A 0.9V low-power 0.4–6GHz linear SDR receiver in 28nm CMOS

Jonathan Borremans, Jan Craninckx, Ewout Martens, 2013, 2013 Symposium on VLSI Circuits.

High-level modeling and synthesis of analog integrated systems ; Hoog-niveau synthese van analoge geïntegreerde systemen

Ewout Martens, 2007 .

Efficient time-domain simulation of continuous-time /spl Delta//spl Sigma/ A/D converters using analytical integration

Georges G. E. Gielen, Ewout Martens, Kenneth Francken, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A 0.7–1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection

Jan Craninckx, Piet Wambacq, Ewout Martens, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Jan Craninckx, Ewout Martens, Nick Van Helleputte, 2019, IEEE Transactions on Biomedical Circuits and Systems.

High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models

Georges G. E. Gielen, Ewout Martens, 2004, ASP-DAC.

Time-domain simulation of sampled weakly nonlinear systems using analytical integration and orthogonal polynomial series [mixed-signal IC applications]

Georges G. E. Gielen, Ewout Martens, 2005, Design, Automation and Test in Europe.

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm

Jan Craninckx, Ewout Martens, Nereo Markulic, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Jonathan Borremans, Jan Craninckx, Ewout Martens, 2014, IEEE Journal of Solid-State Circuits.

Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models

Georges G. E. Gielen, Ewout Martens, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

Jan Craninckx, Andre Bourdoux, Julien Ryckaert, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

High-Level Modeling and Synthesis of Analog Integrated Systems

Georges Gielen, Ewout Martens, 2008 .

A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers

Jan Craninckx, Piet Wambacq, Ewout Martens, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Generic Behavioral Modeling of Analog and Mixed-Signal Systems

Georges G. E. Gielen, Ewout Martens, 2006, FDL.

A model of computation for continuous-time /spl Delta//spl Sigma/ modulators

Georges G. E. Gielen, Ewout Martens, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2017, 2017 Symposium on VLSI Circuits.

IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm

Jonathan Borremans, Jan Craninckx, Ewout Martens, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE Journal of Solid-State Circuits.

A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems

Georges G. E. Gielen, Ewout Martens, G. Gielen, 2006, Proceedings of the Design Automation & Test in Europe Conference.

High level modeling anf dynthesis of analog integrated system

Georges Gielen, Ewout Martens, 2008 .

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Journal of Solid-State Circuits.

ANTIGONE: Top-down creation of analog-to-digital converter architectures

Georges G. E. Gielen, Ewout Martens, 2009, Integr..

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE J. Solid State Circuits.

A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET

Jan Craninckx, Ewout Martens, Davide Dermit, 2020, IEEE Solid-State Circuits Letters.

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Jan Craninckx, Takaya Yamamoto, Ewout Martens, 2015, IEEE Journal of Solid-State Circuits.

9.7 a self-calibrated 10mb/s phase modulator with -37.4db evm based on a 10.1-to-12.4ghz, -246.6db-fom, fractional-n subsampling pll

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Classification of analog synthesis tools based on their architecture selection mechanisms

Georges G. E. Gielen, Ewout Martens, G. Gielen, 2008, Integr..

A phase-frequency transfer description of analog and mixed-signal front-end architectures for system-level design

Georges G. E. Gielen, Ewout Martens, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization

Jan Craninckx, Ewout Martens, Benjamin Hershberg, 2017, 2017 Symposium on VLSI Circuits.

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

Jan Craninckx, Ewout Martens, Benjamin Hershberg, 2018, IEEE Journal of Solid-State Circuits.

DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators

Georges G. E. Gielen, Ewout Martens, Kenneth Francken, 2002, DATE.

Behavioral modeling and simulation of weakly nonlinear sampled-data systems

Georges G. E. Gielen, Ewout Martens, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC

Jan Craninckx, Ewout Martens, Davide Dermit, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

Rui P. Martins, Jan Craninckx, Chi-Hang Chan, 2021, IEEE Journal of Solid-State Circuits.

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC

Rui Paulo Martins, Jan Craninckx, Chi-Hang Chan, 2021, 2021 Symposium on VLSI Circuits.

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2021, 2021 Symposium on VLSI Circuits.

Asynchronous Event-Driven Clocking and Control in Pipelined ADCs

Jan Craninckx, Ewout Martens, Jorge Lagos, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm

Jan Craninckx, Ewout Martens, Jorge Lagos, 2021, IEEE Journal of Solid-State Circuits.

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC

Jan Craninckx, Piet Wambacq, Ewout Martens, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion

Jan Craninckx, Ewout Martens, Jorge Lagos, 2021, IEEE Journal of Solid-State Circuits.

A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Transactions on Microwave Theory and Techniques.