Ben A. Abderazek

发表

LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture

Akram Ben Ahmed, Ben A. Abderazek, B. Abderazek, 2012, 2012 IEEE 6th International Symposium on Embedded Multicore SoCs.

An Efficient Software-Hardware Design Framework for Spiking Neural Network Systems

Ben A. Abderazek, Khanh N. Dang, K. Dang, 2019, 2019 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC).

Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model

Ben A. Abderazek, Hiroki Hoshino, Kenichi Kuroda, 2008, 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing.

New Code Generation Algorithm for QueueCore An Embedded Processor with High ILP

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007 .

The QC-2 parallel Queue processor architecture

Tsutomu Yoshinaga, Arquimedes Canedo, Masahiro Sowa, 2008, J. Parallel Distributed Comput..

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

Ben A. Abderazek, Khanh N. Dang, Yuichi Okuyama, 2016, The Journal of Supercomputing.

Efficient compilation for queue size constrained queue processors

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2009, Parallel Comput..

Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems

Ben A. Abderazek, Khanh N. Dang, Yuichi Okuyama, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Report on power, thermal and reliability prediction for 3D Networks-on-Chip pdf

Ben A. Abderazek, Khanh N. Dang, Xuan-Tu Tran, 2020, ArXiv.

Towards smart health monitoring system for elderly people

Ben A. Abderazek, Achraf Ben Ahmed, Yumiko Kimezawa, 2012, 4th International Conference on Awareness Science and Technology.

Low-overhead Routing Algorithm for 3D Network-on-Chip

Akram Ben Ahmed, Ben A. Abderazek, 2012, 2012 Third International Conference on Networking and Computing.

Proposal and Design of a Parallel Queue Processor Architecture (PQP)

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2002, IASTED PDCS.

Optimizing Reaching Definitions Overhead in Queue Processors

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007, J. Convergence Inf. Technol..

A new code generation algorithm for 2-offset producer order queue computation model

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2008, Comput. Lang. Syst. Struct..

On the Design of a Fault-Tolerant Photonic Network-on-Chip

Yuki Tanaka, Akram Ben Ahmed, Ben A. Abderazek, 2015, 2015 IEEE International Conference on Systems, Man, and Cybernetics.

Multicore Systems On-Chip: Practical Software/Hardware Design

Ben A. Abderazek, B. Abderazek, 2010, Atlantis Ambient and Pervasive Intelligence.

Advanced Multicore Systems-On-Chip

Ben A. Abderazek, B. Abderazek, 2017, Springer Singapore.

Compiler Support for Code Size Reduction Using a Queue-Based Processor

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2009, Trans. High Perform. Embed. Archit. Compil..

Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithm and Architecture for 3D-NoC of Spiking Neurons

Ben A. Abderazek, Yuichi Okuyama, The H. Vu, 2019, ACM J. Emerg. Technol. Comput. Syst..

Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems

Ben A. Abderazek, Yuichi Okuyama, Michael Conrad Meyer, 2017, The Journal of Supercomputing.

Dual-Execution Mode Processor Architecture For Embedded Applications

Masahiro Sowa, Ben A. Abderazek, Md. Musfiquzzaman Akanda, 2007, J. Mobile Multimedia.

Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

Akram Ben Ahmed, Ben A. Abderazek, 2013, The Journal of Supercomputing.

On the Design of a Register Queue Based Processor Architecture (FaRM-rq)

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2003, ISPA.

Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems

Akram Ben Ahmed, Ben A. Abderazek, 2016, J. Parallel Distributed Comput..

Design and architecture for an embedded 32-bit QueueCore

Masahiro Sowa, Ben A. Abderazek, Sotaro Kawata, 2006, J. Embed. Comput..

Theoretical Evaluation of Simultaneous Multithreading Para Ilel Queue Processor Architecture

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2004 .

Scalable core-based methodology and synthesizable core for systematic design environment in multicore SoC (MCSoC)

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2006, 2006 International Conference on Parallel Processing Workshops (ICPPW'06).

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

Ben A. Abderazek, Khanh N. Dang, Xuan-Tu Tran, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Compiling for Reduced Bit-Width Queue Processors

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2010, J. Signal Process. Syst..

Quantitative Evaluation of Common Subexpression Elimination on Queue Machines

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2008, 2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008).

Advanced Design Issues for OASIS Network-on-Chip Architecture

Ben A. Abderazek, Kenichi Kuroda, Kenichi Mori, 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007, EUC.

Dual-execution mode processor architecture

Masahiro Sowa, Ben A. Abderazek, Md. Musfiquzzaman Akanda, 2008, The Journal of Supercomputing.

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2005, EUC.

Parallel Queue Processor Architecture Based on Produced Order Computation Model

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2005, The Journal of Supercomputing.

An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records

Ben A. Abderazek, Kenichi Kuroda, Yasuyoshi Haga, 2010, 2010 39th International Conference on Parallel Processing Workshops.

Architecture and design of real-time system for elderly health monitoring

Ben A. Abderazek, Achraf Ben Ahmed, 2017, Int. J. Embed. Syst..

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

Akram Ben Ahmed, Ben A. Abderazek, Kenichi Kuroda, 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.

Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

Akram Ben Ahmed, Ben A. Abderazek, B. Abderazek, 2014, J. Parallel Distributed Comput..

A Power Estimation Method for Mesh-Based Photonic NoC Routing Algorithms

Ben A. Abderazek, Yuichi Okuyama, Michael Conrad Meyer, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era

Akram Ben Ahmed, Ben A. Abderazek, Takayuki Ochi, 2013, 2013 Seventh International Conference on Complex, Intelligent, and Software Intensive Systems.

ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications

Akram Ben Ahmed, Ben A. Abderazek, Kenichi Mori, 2012, 4th International Conference on Awareness Science and Technology.

Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2005 .

Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems

Akram Ben Ahmed, Ben A. Abderazek, Yuichi Okuyama, 2014, 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs.

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Arquimedes Canedo, Ben A. Abderazek, Kenichi Kuroda, 2011, The Journal of Supercomputing.

An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture

Masahiro Sowa, Ben A. Abderazek, Sotaro Kawata, 2005, EUC.

Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems

Ben A. Abderazek, Yuichi Okuyama, Achraf Ben Ahmed, 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

Single Instruction Dual-Execution Model Processor Architecture

Ben A. Abderazek, Kenichi Kuroda, Taichi Maekawa, 2008, 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing.

C-029 Verilog-HDLによる並列キュープロセッサのデザイン(C.アーキテクチャ・ハードウェア)

繁田聡一, 吉永努, Ben A. Abderazek, 2004 .

Soft-error resilient Network-on-Chip for safety-critical applications

Ben A. Abderazek, Khanh N. Dang, Yuichi Okuyama, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Queue Register File Optimization Algorithm for QueueCore Processor

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007 .

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems

Akram Ben Ahmed, Ben A. Abderazek, Yuichi Okuyama, 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture

Arquimedes Canedo, Ben A. Abderazek, Masashi Masuda, 2009, 2009 International Conference on Parallel Processing Workshops.

Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router

Ben A. Abderazek, Yuichi Okuyama, Michael Conrad Meyer, 2015, 2015 IEEE International Conference on Systems, Man, and Cybernetics.

Performance Enhancement for Matrix Multiplication on an SMP PC Cluster

Tsutomu Yoshinaga, Ben A. Abderazek, Ta Quoc Viet, 2005 .

Proceedings - 2009 International Conference on Embedded Software and Systems, ICESS 2009: Preface

Tianzhou Chen, Dakai Zhu, Walid Taha, 2009, ICESS 2009.

Queue Processor Architecture for Novel Queue Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme Computing Paradigm Based on Produced Order Scheme

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2004 .

SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC

Ben A. Abderazek, Yuichi Okuyama, Michael Conrad Meyer, 2018, The Journal of Supercomputing.

Soft-error resilient 3D Network-on-Chip router

Ben A. Abderazek, Khanh N. Dang, Xuan-Tu Tran, 2015, 2015 IEEE 7th International Conference on Awareness Science and Technology (iCAST).

A Low-latency Tree-based Multicast Spike Routing for Scalable Multicore Neuromorphic Chips

Ben A. Abderazek, The H. Vu, Ogbodo Mark Ikechukwu, 2019, ICIST.

Mathematical Model for Multiobjective Synthesis of NoC Architectures

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2007, 2007 International Conference on Parallel Processing Workshops (ICPPW 2007).

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2006, The Journal of Supercomputing.

QJAVAC: Java Compiler Design for High Parallelism Queue Java Byte Code

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2003 .

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

Ben A. Abderazek, Achraf Ben Ahmed, B. Abderazek, 2015, The Journal of Supercomputing.

Queue Register File Optimization Algorithm for QueueCore Processor

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007, 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07).

Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro inspired Architecture in Hardware

Ben A. Abderazek, Yuichi Okuyama, The H. Vu, 2018, 2018 IEEE International Conference on Big Data and Smart Computing (BigComp).

TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects

Akram Ben Ahmed, Ben A. Abderazek, Khanh N. Dang, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Design and implementation of a queue compiler

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2009, Microprocess. Microsystems.

Low-Latency K-Means Based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips

Ben A. Abderazek, The H. Vu, 2019, 2019 IEEE International Conference on Big Data and Smart Computing (BigComp).

Multicore Systems On-Chip: Practical Software/Hardware Design

Ben A. Abderazek, 2010, Atlantis Ambient and Pervasive Intelligence.

D-6-8 Hybrid Compiler-Controlled Self-Adjustable Parallelism-Independent Scheduling Algorithm for Cluster of Workstations

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2001 .

New Code Generation Algorithm for QueueCore An Embedded Processor with High ILP

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek, 2007, Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007).

Soft-Error and Hard-fault Tolerant Architecture and Routing Algorithm for Reliable 3D-NoC Systems pdf

Ben A. Abderazek, Khanh N. Dang, Yuichi Okuyama, 2020, ArXiv.

Design of Producer-order Parallel Queue Processor Architecture

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2004 .

Energy-Efficient Spike-Based Scalable Architecture for Next-Generation Cognitive AI Computing Systems

Ben A. Abderazek, Khanh N. Dang, Ogbodo Mark Ikechukwu, 2021, UNet.

On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation

Masahiro Sowa, Ben A. Abderazek, Md. Musfiquzzaman Akanda, 2006, ISPA Workshops.

A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs

Tsutomu Yoshinaga, Masahiro Sowa, Ben A. Abderazek, 2003 .