Stephen B. Furber

发表

Bernabé Linares-Barranco, Luis A. Plana, Teresa Serrano-Gotarredona, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor

Luis A. Plana, Stephen B. Furber, David R. Lester, 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

SpiNNaker—Programming Model

Jim D. Garside, Luis A. Plana, Andrew D. Brown, 2015, IEEE Transactions on Computers.

A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect

Luis A. Plana, Stephen B. Furber, Shufan Yang, 2009, Fundam. Informaticae.

Asynchronous macrocell interconnect using MARBLE

William John Bainbridge, Stephen B. Furber, S. Furber, 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors

Andrew D. Brown, Stephen B. Furber, 2009, ACSD.

An asynchronous ternary logic signaling system

Stephen B. Furber, T. Felicijan, 2003, IEEE Trans. Very Large Scale Integr. Syst..

The Amulet chips: Architectural development for asynchronous microprocessors

Jim D. Garside, Steve Temple, Stephen B. Furber, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

MARBLE: an asynchronous on-chip macrocell bus

William John Bainbridge, Stephen B. Furber, S. Furber, 2000, Microprocess. Microsystems.

Notes On Pulse Signaling

Arash Saifhashemi, Stephen B. Furber, Jo C. Ebergen, 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

An asynchronous on-chip network router with quality-of-service (QoS) support

Stephen B. Furber, Tomaz Feliciian, S. Furber, 2004, IEEE International SOC Conference, 2004. Proceedings..

An asynchronous copy-back cache architecture

Jim D. Garside, Stephen B. Furber, Daranee Hormdee, 2003, Microprocess. Microsystems.

AMULET1: a micropipelined ARM

Jim D. Garside, Paul Day, Stephen B. Furber, 1994, Proceedings of COMPCON '94.

Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language

Stephen B. Furber, Philip Endecott, S. Furber, 1998, ESM.

pyDVS: An extensible, real-time Dynamic Vision Sensor emulator using off-the-shelf hardware

Patrick Camilleri, Qian Liu, Stephen B. Furber, 2016, 2016 IEEE Symposium Series on Computational Intelligence (SSCI).

A low-power self-timed Viterbi decoder

Stephen B. Furber, Linda E. M. Brackenbury, P. A. Riocreux, 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

Reliable computation with unreliable computers

Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, 2015, IET Comput. Digit. Tech..

Maximising information recovery from rank-order codes

Stephen B. Furber, Basabdatta Sen Bhattacharya, S. Furber, 2007, SPIE Defense + Commercial Sensing.

An investigation into the security of self-timed circuits

Luis A. Plana, Stephen B. Furber, Z. C. Yu, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

Adaptive admission control on the SpiNNaker MPSoC

Luis A. Plana, Stephen B. Furber, Shufan Yang, 2009, 2009 IEEE International SOC Conference (SOCC).

The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics

Yijun Liu, Stephen B. Furber, S. Furber, 2005, PATMOS.

Design and analysis of a self-timed duplex communication system

Alexandre Yakovlev, Stephen B. Furber, Alexandre V. Bystrov, 2004, IEEE Transactions on Computers.

Sparse distributed memory using N-of-M codes

Steve Temple, Stephen B. Furber, John Bainbridge, 2004, Neural Networks.

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System

Javier Navaridas, Mikel Luján, Luis A. Plana, 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro, 2005, ICANN.

Power Management in the Amulet Microprocessors

Aristides Efthymiou, Jim D. Garside, Steve Temple, 2001, IEEE Des. Test Comput..

Delay-insensitive, point-to-point interconnect using m-of-n codes

William B. Toms, William John Bainbridge, David A. Edwards, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

A forecast-based STDP rule suitable for neuromorphic implementation

Francesco Galluppi, Stephen B. Furber, Alexander D. Rast, 2012, Neural Networks.

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery

Jim D. Garside, David M. Clark, Luis A. Plana, 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

Sparse Distributed Memory Using Rank-Order Neural Codes

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro, 2007, IEEE Transactions on Neural Networks.

AMULET3i-an asynchronous system-on-chip

Siamak Mohammadi, Jim D. Garside, David M. Clark, 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Bernabé Linares-Barranco, Luis A. Plana, Teresa Serrano-Gotarredona, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis

Mark Zwolinski, Zhenyu Liu, A. Asenov, 2011, 2011 Design, Automation & Test in Europe.

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network

Javier Navaridas, Mikel Luján, Luis A. Plana, 2010, Conf. Computing Frontiers.

Four-phase micropipeline latch control circuits

Paul Day, Stephen B. Furber, 1996, IEEE Trans. Very Large Scale Integr. Syst..

A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro, 2005, WIRN/NAIS.

Spiking Associative Memory for Spatio-Temporal Patterns pdf

Oliver Rhodes, Stephen B. Furber, Simon Davidson, 2020, ArXiv.

Asynchronous Embedded Control

Jim D. Garside, Steve Temple, Paul Day, 1998, Integr. Comput. Aided Eng..

The design of an asynchronous VHDL synthesizer

Stephen B. Furber, Wen-Fang Yen, Sun-Yen Tan, 1998, Proceedings Design, Automation and Test in Europe.

AMULET2e: an asynchronous embedded controller

Jim D. Garside, Jianwei Liu, Steve Temple, 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Processing with a million cores

Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, 2011, PARCO.

Validating the AMULET Microprocessors

Stephen B. Furber, 2002, Comput. J..

Jim D. Garside, Paul Day, Stephen B. Furber, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Scan testing of micropipelines

Stephen B. Furber, O. A. Petlin, S. Furber, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors

Stephen B. Furber, 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.

Interconnection system for the spiNNaker biologically inspired multi-computer

Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, 2013, IET Comput. Digit. Tech..

AMULET3: a 100 MIPS asynchronous embedded processor

Jim D. Garside, David A. Edwards, Stephen B. Furber, 2000, Proceedings 2000 International Conference on Computer Design.

Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system

Cameron Patterson, Luis A. Plana, Francesco Galluppi, 2010, Conf. Computing Frontiers.

A GALS Infrastructure for a Massively Parallel Multiprocessor

Luis A. Plana, Jian Wu, Steve Temple, 2007, IEEE Design & Test of Computers.

Built-in self-testing of micropipelines

Stephen B. Furber, O. A. Petlin, S. Furber, 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

The return of asynchronous logic

Stephen B. Furber, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Event-driven MLP implementation on neuromimetic hardware

Luis A. Plana, Stephen B. Furber, Alexander D. Rast, 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

Chain: A Delay-Insensitive Chip Area Interconnect

Stephen B. Furber, John Bainbridge, S. Furber, 2002, IEEE Micro.

A low power embedded dataflow coprocessor

Yijun Liu, Stephen B. Furber, S. Furber, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis

Stephen B. Furber, Basabdatta Sen Bhattacharya, S. Furber, 2010, IEEE Transactions on Neural Networks.

Minimizing the Power Consumption of an Asynchronous Multiplier

Yijun Liu, Stephen B. Furber, S. Furber, 2004, PATMOS.

Efficient modelling of spiking neural networks on a scalable chip multiprocessor

Stephen B. Furber, Xin Jin, J. V. Woods, 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

The design and evaluation of an asynchronous microprocessor

Jim D. Garside, Steve Temple, Paul Day, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

AMULET1: A Asynchronous ARM Microprocessor

Jim D. Garside, Steve Temple, Paul Day, 1997, IEEE Trans. Computers.

The design of a low power asynchronous multiplier

Yijun Liu, Stephen B. Furber, S. Furber, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

An efficient SpiNNaker implementation of the Neural Engineering Framework

Stephen B. Furber, Terrence C. Stewart, Andrew Mundy, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

A micropipelined ARM

Jim D. Garside, Paul Day, Stephen B. Furber, 1993, VLSI.

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM

Michael F. P. O'Boyle, Paul H. J. Kelly, Mikel Luján, 2014, 2015 IEEE International Conference on Robotics and Automation (ICRA).

Dynamic logic in four-phase micropipelines

Jianwei Liu, Stephen B. Furber, S. Furber, 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

AMULET3: a high-performance self-timed ARM microprocessor

Jim D. Garside, Stephen B. Furber, D. A. Gilbert, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Scan testing of asynchronous sequential circuits

Stephen B. Furber, O. A. Petlin, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

Virtual synaptic interconnect using an asynchronous network-on-chip

Stephen B. Furber, Muhammad Mukaram Khan, Alexander D. Rast, 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware

Mikel Luján, Luis A. Plana, Stephen B. Furber, 2010, 2010 Ninth International Symposium on Parallel and Distributed Computing.

Event-based neural computing on an autonomous mobile platform

Luis A. Plana, Jörg Conradt, Francesco Galluppi, 2014, 2014 IEEE International Conference on Robotics and Automation (ICRA).

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

William John Bainbridge, Stephen B. Furber, S. Furber, 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric

Cameron Patterson, Javier Navaridas, Mikel Luján, 2011, Parallel Comput..

VLSI Risc Architecture and Organization

Stephen B. Furber, Stephen B. Furber, 1989 .

On-chip and inter-chip networks for modeling large-scale neural systems

Andrew D. Brown, Steve Temple, Stephen B. Furber, 2006, 2006 IEEE International Symposium on Circuits and Systems.

An associative memory for the on-line recognition and prediction of temporal sequences

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro, 2005, Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005..

The design and test of a smartcard chip using a CHAIN self-timed network-on-chip

Luis A. Plana, William John Bainbridge, Stephen B. Furber, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

An asynchronous victim cache

Jim D. Garside, Stephen B. Furber, Daranee Hormdee, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.