S. H. Jen

A compact VLSI design for recursive neural networks with hardware annealing capability

Bing J. Sheu, E. Y. Chou, S. H. Jen, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

High-speed memory architectures for multimedia applications

B. J. Sheu, Yoshifumi Oshima, S. H. Jen, 1997 .

Two-dimensional cellular neural networks for pre-processing in face recognition and digital library search

S. H. Jen, M. Y. Wang, R. H. Tsai, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz

S. H. Jen, B. Sheu, C. Enz, 1999 .

An efficient MOS transistor charge/capacitance model with continuous expressions for VLSI

Bing J. Sheu, S. H. Jen, A. Y. Park, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

An improved method for MOS transistor output conductance

S. H. Jen, B. Sheu, Y. Oshima, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs

Bing J. Sheu, S. H. Jen, Steve H. Jen, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Bing J. Sheu, Steve H. Jen, Christian Enz, 2000 .