Mitsuo Yasuhira

Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

Shoji Ikeda, Hiroki Koike, Tetsuo Endoh, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 47.14- $\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, IEEE Journal of Solid-State Circuits.

1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

Shoji Ikeda, Hiroki Koike, Tetsuo Endoh, 2015, 2015 IEEE International Memory Workshop (IMW).

Hot Carrier Effect in UltraThin Gate Oxide Metal Oxide Semiconductor Field Effect Transistor

Yukiharu Uraoka, Hiroyuki Honda, Mitsuo Yasuhira, 2005 .

A 0.1 /spl mu/m CMOS with a step channel profile formed by ultra high vacuum CVD and in-situ doped ions

Atsushi Hori, Mitsuo Yasuhira, H. Umimoto, 1993, Proceedings of IEEE International Electron Devices Meeting.

High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

Atsushi Hori, Mitsuo Yasuhira, Mizuki Segawa, 1993 .

Critical Role of W Insertion Layer Sputtering Condition for Reference Layer on Magnetic and Transport Properties of Perpendicular-Anisotropy Magnetic Tunnel Junction

Shoji Ikeda, Tetsuo Endoh, Hiroaki Honjo, 2019, IEEE Transactions on Magnetics.