T. Serrano-Gotarredona

发表

Fully-parallel Convolutional Neural Network Hardware pdf

Christiam F. Frasser, Pablo Linares-Serrano, V. Canals, 2020, ArXiv.

A mismatch characterization and simulation environment for weak-to-strong inversion CMOS transistors

T. Serrano-Gotarredona, B. Linares-Barranco, J. Velarde-Ramirez, 2005, SPIE Microtechnologies.

An ART1 microchip and its use in multi-ART1 systems

T. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems

T. Serrano-Gotarredona, B. Linares-Barranco, T. Prodromakis, 2013, IEEE Circuits and Systems Magazine.

Experimental results on the current-mode WTA-MAX circuit with multi-chip capability

T. Serrano-Gotarredona, B. Linares-Barranco, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A 100dB dynamic range event-driven spatial contrast sensor with 100μs response time and Time-to-First-Spike mode

T. Serrano-Gotarredona, B. Linares-Barranco, J. A. Lenero-Bardallo, 2010, 2010 Proceedings of ESSCIRC.

Design of adaptive nano/CMOS neural architectures

T. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

MOS/bipolar active input current mirrors with 13–decades gain adjustment range

T. Serrano-Gotarredona, B. Linares-Barranco, A.G. Andreou, 1998, Proceedings of the 24th European Solid-State Circuits Conference.

Event-driven stereo vision with orientation filters

T. Serrano-Gotarredona, B. Linares-Barranco, R. Benosman, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Reliable handling of fempto-ampere currents in standard CMOS

T. Serrano-Gotarredona, B. Linares-Barranco, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

Systematic CMOS transistor mismatch characterization

T. Serrano-Gotarredona, B. Linares-Barranco, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

STDP and STDP variations with memristors for spiking neuromorphic learning systems

T. Serrano-Gotarredona, B. Linares-Barranco, T. Prodromakis, 2013, Front. Neurosci..

A 'do-it-yourself' methodology for CMOS transistor mismatch characterization

T. Serrano-Gotarredona, B. Linares-Barranco, 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

A loss control feedback loop for VCO stable amplitude tuning of RF integrated filters

T. Serrano-Gotarredona, B. Linares-Barranco, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

CMOS transistor mismatch model valid from weak to strong inversion

T. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A 5-parameter mismatch model for short channel MOS transistors

T. Serrano-Gotarredona, B. Linares-Barranco, 1999, Proceedings of the 25th European Solid-State Circuits Conference.

Programmable 2D image filter for AER vision processing

T. Serrano-Gotarredona, B. Linares-Barranco, A.G. Andreou, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Fast and compact simulation models for a variety of FET nano devices by the CMOS EKV equations

T. Serrano-Gotarredona, B. Linares-Barranco, D. Vuillaume, 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

A STORED PROGRAM 2ND ORDERb-LAYER COMPLEX CELL CNN-ui"l

T. Serrano-Gotarredona, T. Roska, A. Rodriguez-Vbzquez, 2000 .

MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

T. Serrano-Gotarredona, D. Flandre, L. Vancaillie, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A stored program 2/sup nd/ order/3-layer complex cell CNN-UM

T. Serrano-Gotarredona, A. Rodriguez-Vazquez, C. Rekeczky, 2000, Proceedings of the 2000 6th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2000) (Cat. No.00TH8509).

A Bio-inspired Event-Based Real-Time Image Processor

T. Serrano-Gotarredona, B. Linares-Barranco, R. Serrano-Gotarredona, 2006, The First IEEE/RAS-EMBS International Conference on Biomedical Robotics and Biomechatronics, 2006. BioRob 2006..

Cheap and easy systematic CMOS transistor mismatch characterization

T. Serrano-Gotarredona, B. Linares-Barranco, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

A 2D image filtering architecture for real-time vision processing systems

T. Serrano-Gotarredona, B. Linares-Barranco, A.G. Andreou, 1999, Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems.

A new 5-parameter MOS transistors mismatch model

T. Serrano-Gotarredona, B. Linares-Barranco, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Passive localization and detection of quadcopter UAVs by using dynamic vision sensor

T. Serrano-Gotarredona, B. Linares-Barranco, A. Yousefzadeh, 2017, 2017 5th Iranian Joint Congress on Fuzzy and Intelligent Systems (CFIS).

Voltage clamping current mirrors with 13-decades gain adjustment range suitable for low power MOS/bipolar current mode signal processing circuits

T. Serrano-Gotarredona, B. Linares-Barranco, A.G. Andreou, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Exploiting Correlation in Stochastic Computing based Deep Neural Networks

Christiam F. Frasser, Pablo Linares-Serrano, V. Canals, 2021, 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS).

Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices

T. Serrano-Gotarredona, B. Linares-Barranco, J. M. de la Rosa, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Exploiting memristance in adaptive asynchronous spiking neuromorphic nanotechnology systems

T. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

A new five-parameter MOS transistor mismatch model

T. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, 2000, IEEE Electron Device Letters.