Ichiro Nakao

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A. Ueno, Hiroyuki Yamauchi, Toshio Yamada, 1988 .

A semiconductor device comprising memory chip and the memory peripheral circuit chip and manufacturing processes

Tsutomu Fujita, Reiji Segawa, Toshiki Mori, 1995 .

Numerical modeling of nonplanar oxidation coupled with stress effects

Shinji Odanaka, Hiroyuki Umimoto, Hideya Esaki, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Monolithic Integration of InGaAsP/InP Laser Diode with Heterojunction Bipolar Transistors

Hiroyuki Serizawa, Yoichi Sasai, Jun Shibata, 1984 .

SCC (Surrounded Capacitor Cell) Structure for DRAM

Shinji Odanaka, Toshio Yamada, T. Ohzone, 1987 .