N. Aoi

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A. Ueno, Hiroyuki Yamauchi, Toshio Yamada, 1988 .

Integration of 3 level air gap interconnect for sub-quarter micron CMOS

H. Sato, T. Ueda, K. Yamashita, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A novel clustered hard mask technology for dual damascene multilevel interconnects with self-aligned via formation using an organic low k dielectric

T. Ueda, N. Aoi, E. Tamaoka, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Evaluation and analysis for mechanical strengths of low k dielectrics by a finite element method

N. Aoi, H. Yanazawa, Takuya Fukuda, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).