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A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

E. P. Martin, A. L. Brooks, I. C. Kizilyalli, 1996, Proceedings of Custom Integrated Circuits Conference.

High performance 3.3 and 5 volt 0.5-/spl mu/m CMOS technologies for ASICs

E. P. Martin, I. C. Kizilyalli, M. Twiford, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

High performance 3.3- and 5-V 0.5-/spl mu/m CMOS technology for ASIC's

I. C. Kizilyalli, M. Twiford, E. P. Martin, 1995 .

Predictive worst case statistical modeling of 0.8- mu m BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

I. C. Kizilyalli, M. J. Thoma, K. Singhal, 1993 .

A 0.8-/spl mu/m BiCMOS technology for ASIC applications

J. W. Osenbach, D. M. Boulin, M. J. Thoma, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.