P. Vandervoorn

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.

A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

S.-J. Choi, W. Hafez, M. Kang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

S. Natarajan, M. Agostinelli, C. Tsai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

J. Lee, K. Komeyli, K. Phoa, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Planar device on gratbasierter transistor architecture

Walid M. Hafez, P. Vandervoorn, Chia-Hing Jan, 2013 .

A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications

P. Packan, M. Hattendorf, I. Post, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..