Payman Behnam

发表

Emerging Hardware Technologies for IoT Data Processing

Mahdi Nazm Bojnordi, Payman Behnam, M. N. Bojnordi, 2020 .

A probabilistic approach for counterexample generation to aid design debugging

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2013, East-West Design & Test Symposium (EWDTS 2013).

Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs

Payman Behnam, Bijan Alizadeh, B. Alizadeh, 2013, Microprocess. Microsystems.

A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression

Payman Behnam, Behjat Forouzandeh, Bijan Alizadeh, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Improving polynomial datapath debugging with HEDs

Masahiro Fujita, Zainalabedin Navabi, Payman Behnam, 2014, 2014 19th IEEE European Test Symposium (ETS).

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs

Payman Behnam, Bijan Alizadeh, Somayeh Sadeghi Kohan, 2015, IEEE Transactions on Computers.

Automatic correction of certain design errors using mutation technique

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2014, 2014 19th IEEE European Test Symposium (ETS).

Accelerating $k$ -Medians Clustering Using a Novel 4T-4R RRAM Cell

Payman Behnam, Yomi Karthik Rupesh, Goverdhan Reddy Pandla, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

STFL-DDR: Improving the Energy-Efficiency of Memory Interface

Mahdi Nazm Bojnordi, Payman Behnam, M. N. Bojnordi, 2020, IEEE Transactions on Computers.

RedCache: Reduced DRAM Caching

Mahdi Nazm Bojnordi, Payman Behnam, M. N. Bojnordi, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling

Mahdi Nazm Bojnordi, Payman Behnam, M. N. Bojnordi, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism

M. H. Haghbayan, Payman Behnam, Saeed Safari, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A novel SAT-based ATPG approach for transition delay faults

Zainalabedin Navabi, Payman Behnam, Vahid Janfaza, 2017, 2017 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures

Mahdi Nazm Bojnordi, Payman Behnam, Naser Sedaghati, 2017, E2SC@SC.

R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays

Mahdi Nazm Bojnordi, Payman Behnam, Arjun Pal Chowdhury, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

Validation of Hardware Security and Trust: A Survey pdf

Payman Behnam, 2018, ArXiv.

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms

Payman Behnam, Bijan Alizadeh, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Hybrid history-based test overlapping to reduce test application time

Payman Behnam, Behjat Forouzandeh, Mohammadreza Najafi, 2013, East-West Design & Test Symposium (EWDTS 2013).

Hybrid history-based test overlapping to reduce test application time

Payman Behnam, Behjat Forouzandeh, Mohammadreza Najafi, 2013, EWDTS.

Formally analyzing fault tolerance in datapath designs using equivalence checking

Masahiro Fujita, Payman Behnam, Sajjad Taheri, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs pdf

Payman Behnam, Sajjad Taheri, Bijan Alizadeh, 2017, ArXiv.

Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines

Alexander V. Veidenbaum, Alexandru Nicolau, Payman Behnam, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters

Reza Sameni, Payman Behnam, Eesa Nikahd, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator

Hang Liu, Xuehai Qian, Xiaolong Ma, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators

Xiaolong Ma, Mahdi Nazm Bojnordi, Payman Behnam, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms

Alexander V. Veidenbaum, Alexandru Nicolau, Elaheh Bozorgzadeh, 2019, FPGA.