Satyendranath Mukherjee

Lateral smart-discrete process and devices based on thin-layer silicon-on-insulator

Theodore Letavic, John Petruzzello, Mark Simpson, 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

A method for manufacturing a nonvolatile memory device as grave

Satyendranath Mukherjee, Manjin Kim, 1993 .

600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator

Theodore Letavic, Mark Simpson, J. Curcio, 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).

A scaled CMOS-compatible smart power IC technology

Satyendranath Mukherjee, S. L. Wong, J. C. Young, 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

A high current power IC technology using trench DMOS power device

Satyendranath Mukherjee, J. C. Young, M. Kim, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Electrically erasable and programmable read only memory with non-uniform thickness dieelektrischer

Mark Simpson, Satyendranath Mukherjee, Di-Son Kuo, 1996 .

600 V single-chip power conversion system based on thin layer silicon-on-insulator

Theodore Letavic, Mark Simpson, Satyendranath Mukherjee, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

Comparison of junction-isolated and soi high-voltage devices operating in the source-follower mode

Satyendranath Mukherjee, Steven L. Merchant, Emil Arnold, 1992, Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics.

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

Theodore Letavic, Satyendranath Mukherjee, Steven L. Merchant, 1993, [1993] Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs.