H. Suzuki

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii, H. Makino, H. Notani, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

H. Makino, M. Fujii, H. Notani, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit

T. Shimizu, H. Sato, H. Shinohara, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..