Jean-Didier Legat

发表

SleepWalker: A 25-MHz 0.4-V Sub- $\hbox{mm}^{2}$ 7- $\mu\hbox{W/MHz}$ Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

David Bol, Julien De Vos, Cédric Hocquet, 2013, IEEE Journal of Solid-State Circuits.

An Associative Processor Dedicated to Classification by Neural Methods

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1995, IWANN.

Flexible embedded system for sensor integration and custom data processing in an automotive application

Jean-Didier Legat, Lotfi Guedria, Damien Hubaux, 2009, IWCMC.

Suboptimal Bayesian classification by vector quantization with small clusters

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1995, ESANN.

A generic and parallel VLSI architecture for multiresolution image coding

Jean-Didier Legat, Benoît Macq, Pierre Desneux, 1993 .

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison

David Bol, Jean-Didier Legat, Maria J. Avedillo, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A coarse grain reconfigurable architecture for sensor networks

Jean-Didier Legat, Bertrand Rousseau, Philippe Manet, 2006 .

ULPFA: A New Efficient Design of a Power-Aware Full Adder

Ian O'Connor, Denis Flandre, Jean-Didier Legat, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

A dedicated neural network for visual motion detection

Michel Verleysen, Jean-Didier Legat, Emmanuel Hanssens, 1992 .

Compact and Efficient Encryption / Decryption Module for FPGA Implementation of AES

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2004 .

Channel Length Upsize for Robust and Compact Subthreshold SRAM

David Bol, Denis Flandre, Jean-Didier Legat, 2008 .

A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2018, IEEE Transactions on Biomedical Circuits and Systems.

A real-time VLSI-based architecture for multi-motion estimation

Jean-Didier Legat, Michel Verleysen, J. P. Cornil, 1992, Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,.

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications

David Bol, Jean-Didier Legat, Philippe Manet, 2006, J. Low Power Electron..

A Reconfigurable System for Intelligent Processing At Communication Terminal

Jean-Didier Legat, Christophe Amerijckx, 1998 .

A new processor architecture exploiting ILP with a reduced instruction word

Jean-Didier Legat, Laurent Petit, 1998 .

Green SoCs for a sustainable Internet-of-Things

David Bol, Denis Flandre, Jean-Didier Legat, 2013, 2013 IEEE Faible Tension Faible Consommation.

An efficient metric of setup time for pulsed flip-flops based on output transition time

David Bol, Jean-Didier Legat, Alexandre Valentian, 2013, Proceedings of 2013 International Conference on IC Design & Technology (ICICDT).

Efficient parallelisation of an MPEG-2 codec on a TMS320C80 video processor

Jean-Didier Legat, Olivier Cantineau, 1998, Proceedings 1998 International Conference on Image Processing. ICIP98 (Cat. No.98CB36269).

An associative processor architecture for pattern recognition

Jean-Didier Legat, Philippe Thissen, Michel Verleysen, 1995 .

Programmable architectures for subband coding : FPGA-based systems versus dedicated VLSI chip

Jean-Didier Legat, Pierre Desneux, Jean-Pierre David, 1998 .

Analog implementation of a Kohonen map with on-chip learning

Michel Verleysen, Jean-Didier Legat, Paul G. A. Jespers, 1993, IEEE Trans. Neural Networks.

A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications

Jean-Didier Legat, Angelo Kuti Lusala, 2012, 10th IEEE International NEWCAS Conference.

A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Combining sdm-based circuit switching with packet switching in a NoC for real-time applications

Jean-Didier Legat, Angelo Kuti Lusala, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

An adaptive pre-processing for on-line hand-written character recognition by blind people

Yves Deville, Jean-Didier Legat, Renaud de Saint Moulin, 1998 .

Hardware Virtualization in FPGA for Software Defined Radion

Jean-Didier Legat, Philippe Manet, Marc Baltus, 2006 .

AGADDIS : Authentication and Geometrical Attacks Detection for Digital Image Signature

Jean-Didier Legat, Benoît Macq, Frédéric Lefebvre, 2002 .

Optimum Weighted Signal-Adapted Biorthogonal Wavelet Transform for Multiresolution Image Coding

Jean-Didier Legat, Benoît Macq, Jean-Yves Mertes, 1993 .

A FPGA-Based Implementation of Adaptive Sound Filtering

Jean-Didier Legat, Jean-Pierre David, 1998 .

Hardware security for software privacy support

Jean-Didier Legat, Jean-Jacques Quisquater, Tanguy Gilmont, 1999 .

Architecture synchronisée par les données pour systèmes reconfigurables

Jean-Didier Legat, Jean-Pierre David, J. David, 2001 .

Mise en oeuvre d'un NoC avec QoS à l'aide des circuits virtuels

Jean-Didier Legat, Philippe Manet, Vital Angelo Kuti Lusala Tsumbu-Mbi, 2008 .

Design and implementation of a remapping algorithm for visual prosthesis.

Jean-Didier Legat, Christophe Amerijckx, Charles Trullemans, 1999 .

AStErIx : An Interactive Environment for Logic Synthesis and Analysis

Jean-Didier Legat, Christophe Amerijckx, Ricardo Ferreira, 1998 .

Analysis and minimization of practical energy in 45nm subthreshold logic circuits

David Bol, Denis Flandre, Jean-Didier Legat, 2008, 2008 IEEE International Conference on Computer Design.

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices

David Bol, Denis Flandre, Jean-Didier Legat, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A statistical neural network for high-dimensional vector classification

Jean-Didier Legat, Philippe Thissen, Jean-Luc Voz, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

A SDM-TDM based circuit-switched router for on-chip networks

Jean-Didier Legat, Angelo Kuti Lusala, 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

Enhancing security in the memory management unit

Jean-Didier Legat, Jean-Jacques Quisquater, Tanguy Gilmont, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Branch-Based Design of Carry Calculation Cell for Ultra-Low Power and High-Temperature Applications

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2004 .

Scaling method for linear-phase lattice filters for multiresolution image coding

Jean-Didier Legat, P. Desneux, J. Y. Mertes, 1994, Other Conferences.

Application-based workload model for wireless sensor node computing platforms

Jean-Didier Legat, Hans Vandierendonck, Philippe Manet, 2011, 2011 Faible Tension Faible Consommation (FTFC).

A SDM-TDM based circuit-switched router for on-chip networks

Jean-Didier Legat, Angelo Kuti Lusala, 2011, ReCoSoC.

An on-line hand-written character recognition system dedicated to blind people

Jean-Didier Legat, Y. Deville, R. de Saint Moulin, 1998 .

A FPGA-based control unit for dedicated parallel processor

Jean-Didier Legat, Philippe Thissen, Michel Verleysen, 1995 .

Enabling certification for dynamic partial reconfiguration using a minimal flow

Jean-Didier Legat, Bertrand Rousseau, Philippe Manet, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2004, FSE.

Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits

Kaushik Roy, David Bol, François Botman, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Parallel Coprocessor Architecture for Binary Image Processing

Jean-Didier Legat, Pierre De Muelenaere, 1991 .

A data-flow oriented co-design for reconfigurable systems

Jean-Didier Legat, Jean-Pierre David, 1998, Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237).

Systolic implementation of a bidimensional lattice filter bank for multiresolution image coding

Jean-Didier Legat, P. Desneux, J. Y. Mertes, 1993, Other Conferences.

Word-parallel CRC computation on VLIW DSP

Jean-Didier Legat, Damien Hubaux, 2002 .

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI

David Bol, Jean-Didier Legat, Alexandre Valentian, 2016, Microelectron. J..

Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology

David Bol, Jean-Didier Legat, Alexandre Valentian, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Efficient FPGA Implementations of Block Ciphers KHAZAD and MISTY1

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002 .

Adaptation of Cyclic Redundancy Check Computation to a VLIW Architecture

Jean-Didier Legat, Damien Hubaux, 2002 .

Image compression by self-organized Kohonen map

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1998, IEEE Trans. Neural Networks.

An efficient FPGA implementation of a flexible JPEG2000 decoder for Digital Cinema

Antonin Descampe, Jean-Didier Legat, Benoit M. Macq, 2004, 2004 12th European Signal Processing Conference.

Using Dynamic Reconfiguration of FPGA for telecommunication applications

Jean-Didier Legat, Bertrand Rousseau, Philippe Manet, 2006 .

Optimal decision surfaces in LVQ1 classiffication of patterns

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1993, ESANN.

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits

David Bol, Cédric Hocquet, Denis Flandre, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

The ATHIS project: Advanced Techniques for High-Temperature System-on-Chip

Denis Flandre, Jean-Didier Legat, X. Jorda, 2005 .

A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications

Jean-Didier Legat, Angelo Kuti Lusala, 2010, NORCHIP 2010.

High Temperature Characterization of a Low Power HT SOI 80C51

David Bol, Jean-Didier Legat, Philippe Manet, 2006 .

Une procédure d'initialisation de type LVQ pour le réseau RCE

Jean-Didier Legat, Michel Verleysen, 1992 .

Assessment of 65nm subthreshold logic for smart RFID applications

David Bol, Cédric Hocquet, Jean-Didier Legat, 2009 .

Practical evaluation of a radial soft hash algorithm

Jean-Didier Legat, Benoit M. Macq, Jean-Jacques Quisquater, 2005, International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II.

A fully-synthesized 20-gate digital spike-based synapse with embedded online learning

David Bol, Jean-Didier Legat, Giacomo Indiveri, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Interests and Limitations of Technology Scaling for Subthreshold Logic

David Bol, Denis Flandre, Jean-Didier Legat, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of a processor dedicated to AC motor control in a multiprocessor structure

Jean-Didier Legat, Francis Labrique, Damien Grenier, 2001 .

Analog storage of adjustable synaptic weights

Jean-Didier Legat, Paul Jespers, D. Macq, 1992, Defense, Security, and Sensing.

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes

David Bol, Julien De Vos, François Botman, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A New Active Skeletal Model for Shape Description

Jean-Didier Legat, Benoît Macq, Olivier Cantineau, 1998 .

A hybrid router combining circuit switching and packet switching with bus architecture for on-chip networks

Jean-Didier Legat, Angelo Kuti Lusala, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

VLIW processor architecture adapted to FPAs

Jean-Didier Legat, Laurenne Petit, J. Legat, 1998, Other Conferences.

Parallel VLSI-based architecture for multimotion estimation

Jean-Didier Legat, J. P. Cornil, Damien Macq, 1992, Defense, Security, and Sensing.

Evaluation of dynamic partial reconfiguration in professional electronics applications

Jean-Didier Legat, Christian Gamrat, Philippe Manet, 2007 .

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic

David Bol, Denis Flandre, Jean-Didier Legat, 2009, ISLPED.

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2004, PATMOS.

An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications

Jean-Didier Legat, Christian Gamrat, Bertrand Rousseau, 2008, EURASIP J. Embed. Syst..

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

Jean-Didier Legat, Angelo Kuti Lusala, 2012, Int. J. Reconfigurable Comput..

Selective prediction error transmission using motion information

Jean-Didier Legat, Bertrand Chupeau, Benoit M. Macq, 1998, Signal Process. Image Commun..

SEE evaluation of a low-power 1μm-SOI 80C51 for extremely harsh environments

Jean-Didier Legat, Philippe Manet, Sebastien Falmagne, 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2005 .

MOBILE Digital Circuits based on Negative-Differential-Resistance MOS Structures

David Bol, Jean-Didier Legat, José M. Quintana, 2006 .

Ultra-low-power circuits

David Bol, Denis Flandre, Jean-Didier Legat, 2010 .

Analog implementation of an associative memory: learning algorithm and VLSI constraints

Jean-Didier Legat, Paul Jespers, Michel Verleysen, 1993 .

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

David Bol, Julien De Vos, Denis Flandre, 2008 .

A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000

Jean-Didier Legat, Olivier Cantineau, Benoît Georis, 2003, IEEE Trans. Circuits Syst. Video Technol..

Design techniques for reliable timing closure in ULV SoCs

David Bol, Julien De Vos, Cédric Hocquet, 2011 .

Hardware techniques for the real-time implementation of image processing algorithms.

Jean-Didier Legat, Laurent Petit, 1999 .

A VLSI System for Neural Bayesian and LVQ Classification

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1995, IWANN.

Optimisation de la logique différentielle adiabatique ADCVSL par utilisation du DTMOS

Jean-Didier Legat, Jean-Didier Legat, 2001 .

RASH: RAdon soft hash algorithm

Jean-Didier Legat, Benoit M. Macq, Frédéric Lefèbvre, 2002, 2002 11th European Signal Processing Conference.

Study of parallelism between memory accesses for multi-banked cache architectures

Jean-Didier Legat, Hans Vandierendonck, Philippe Manet, 2006 .

Optimum lattice multiresolution transform for image compression

Jean-Didier Legat, Serge Comes, J. Y. Mertes, 1992, Other Conferences.

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

David Bol, Cédric Hocquet, Denis Flandre, 2011, Journal of Cryptographic Engineering.

A survey on industrial vision systems, applications, tools

Euripides G. M. Petrakis, Jean-Didier Legat, Elias N. Malamas, 2003, Image Vis. Comput..

A Cooperative Design of a Mixed Analog Digital Coprocessor for Binary Image Capture

Jean-Didier Legat, Paul Jespers, B. Ginetti, 1992 .

NoC Implementation in FPGA using Torus Topology

Jean-Didier Legat, Angelo Kuti Lusala, Bertrand Rousseau, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Architecture of security management unit for safe hosting of multiple agents

Jean-Didier Legat, Jean-Jacques Quisquater, Tanguy Gilmont, 1999, Electronic Imaging.

Impact of Technology Scaling on Digital Subthreshold Circuits

David Bol, Denis Flandre, Jean-Didier Legat, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

LVQ-like procedure for the initialization of the RCE model

Michel Verleysen, Jean-Didier Legat, François Blayo, 1992 .

Trends in Implementing Commuication Terminal Elements

Jean-Didier Legat, 1997 .

RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics

Jean-Didier Legat, Christian Gamrat, Philippe Manet, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

A Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1995, IWANN.

Phomat-2000, a NMOS photosensor with binary output pattern

Jean-Didier Legat, Paul Jespers, Pierre De Muelenaere, 1985 .

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2006, Microelectron. J..

Dynamically Reconfigurable Architectures for Software-Defined Radio in Professional Electronic Applications

Jean-Didier Legat, Bertrand Rousseau, Philippe Manet, 2012 .

Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2003, FPL.

A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks

Jean-Didier Legat, Angelo Kuti Lusala, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes

David Bol, Julien De Vos, Cédric Hocquet, 2012, 2012 IEEE International Solid-State Circuits Conference.

An Hierarchical Ring Network for Embedded Reconfigurable Systems

Jean-Didier Legat, Christophe Amerijckx, J. Legat, 1998 .

Image Compression using self-Organizing Maps

Jean-Didier Legat, Christophe Amerijckx, Michel Verleysen, 2003 .

A Design Methodology for Secured ICs Using Dynamic Current Mode Logic

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2005, PATMOS.

A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002, FPL.

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

Jean-Didier Legat, Hans Vandierendonck, Bertrand Rousseau, 2010, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP).

Full Custom LSI IC for Document Analysis Systems

Jean-Didier Legat, Paul Jespers, Pierre De Muelenaere, 1984, ESSCIRC '84: Tenth European Solid-State Circuits Conference.

A 400Kgates 8Mbytes SRAM multi-FPGA PCI system International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, 16-18/12/1997,1997,5 pp.

Jean-Didier Legat, 1997 .

A Hybrid Full-adder Cell for High-Performance and Low-Power Design

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2004 .

A VLSI Associative Processor for Neural-Like Classification Algorithms

Jean-Didier Legat, Philippe Thissen, Michel Verleysen, 1996 .

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature

David Bol, Jean-Didier Legat, Alexandre Valentian, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

PLL Jitter Behavioral Modeling and Simulation using HDL-A.

Denis Flandre, Jean-Didier Legat, Pierre Delatte, 1999 .

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2019, IEEE Transactions on Biomedical Circuits and Systems.

Design of a Multi-FPGA System for Rapid Prototyping Experimentation

Jean-Didier Legat, Jean-Pierre David, 1998 .

Ultra-Low-Voltage Nanometer CMOS Circuits for Smart Energy- Autonomous Systems

David Bol, Julien De Vos, Cédric Hocquet, 2010 .

A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2015, 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

An FPGA Implementation of the Linear Cryptanalysis

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002, FPL.

A Dynamic Current Mode Logic to Counteract Power Analysis Attacks

Jean-Didier Legat, François-Xavier Standaert, Jean-Jacques Quisquater, 2004 .

VLSI Architectures for Parallel Processing

Jean-Didier Legat, 1994 .

Application of suboptimal Bayesian classification to handwritten numerals recognition

Jean-Didier Legat, Philippe Thissen, Jean-Luc Voz, 1994 .

By-passing the out-of-order execution pipeline to increase energy-efficiency

Jean-Didier Legat, Hans Vandierendonck, Philippe Manet, 2007, CF '07.

Low Power Microcontroller for High Temperature Applications

David Bol, Jean-Didier Legat, Philippe Manet, 2005 .

Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses

Jean-Didier Legat, Hans Vandierendonck, Philippe Manet, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Virtualization analysis of a reconfigurable region for adaptive DSP and multimedia applications

Jean-Didier Legat, Hans Vandierendonck, Bertrand Rousseau, 2008 .

A VLSI coprocessor for binary image processing and features extraction

Jean-Didier Legat, Pierre De Muelenaere, 1991 .

Ultra-Low-Power logic style for low-frequency high-temperature applications

David Bol, Denis Flandre, Jean-Didier Legat, 2008 .

ICT based e-learning of electrical circuits during the first cycle of engineering at UCL

Jean-Didier Legat, Francis Labrique, Sophie Labrique, 2003 .

A VLSI-based SIMD Processor for Binary Pattern Recognition

Jean-Didier Legat, 1992 .

Exploring the Opportunity of Operating a COTS FPGA at 0.5V

David Bol, Cédric Hocquet, François Botman, 2011 .

Combining circuit and packet switching with bus architecture in a NoC for real-time applications

Jean-Didier Legat, Angelo Kuti Lusala, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Comparative study of a synchronous motor current control loop stability, implanted on mono and multiprocessor architectures

Jean-Didier Legat, Francis Labrique, Damien Grenier, 2002 .

A New Parallelism Management Scheme for Multiprocessor Systems

Jean-Didier Legat, Benoit M. Macq, Jean-Jacques Quisquater, 1999, ACPC.

Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2003, CHES.

Dynamic differential self-timed logic families for robust and low-power security ICs

Denis Flandre, Jean-Didier Legat, Ilham Hassoune, 2007, Integr..

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder

David Bol, Denis Flandre, Jean-Didier Legat, 2007, J. Multiple Valued Log. Soft Comput..

Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards

David Bol, Jean-Didier Legat, Jean-Jacques Quisquater, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

A hardware accelerator for image processing applications

Jean-Didier Legat, Laurent Petit, 1999 .

Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2003, IEEE Trans. Computers.

A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2019, IEEE Trans. Biomed. Circuits Syst..

Resolution reduction by growth of zones for visual prosthesis

Jean-Didier Legat, Tanguy Gilmont, Claude Veraart, 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

A Multi-FPGA System for Prototyping Power Conscious Algorithms

Jean-Didier Legat, Jean-Pierre David, Ricardo Ferreira, 2000 .

In Search of an Optimal Signal-Adapted Multiresolution Transform for Image Compression

Jean-Didier Legat, Benoît Macq, Jean-Yves Mertes, 1992 .

Parallel processor for motion estimation

Jean-Didier Legat, Emmanuel Hanssens, 1996, Other Conferences.

Investigation of the routing algorithm in a De Bruijn-based NoC for low-power applications

David Bol, Jean-Didier Legat, Angelo Kuti Lusala, 2013, 2013 IEEE Faible Tension Faible Consommation.

A Flexible Hardware JPEG 2000 Decoder for Digital Cinema

Antonin Descampe, Jean-Didier Legat, Benoit M. Macq, 2006, IEEE Transactions on Circuits and Systems for Video Technology.

Matching properties of CMOS SOI transistors

Jean-Didier Legat, Philippe Thissen, Michel Verleysen, 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

Generation and Parallelization of Multibody System Equations of Motion by a Symbolic Approach

Jean-Didier Legat, Paul Fisette, T Postiau, 2000 .

Opportunité d'utiliser la reconfiguration dynamique pour optimiser la consommation d'applications implémentées en FPGA

Jean-Didier Legat, Philippe Manet, Vital Angelo Kuti Lusala Tsumbu-Mbi, 2007 .

Low Power 80C51 Microcontroller in SOI High Temperature Technology

David Bol, Jean-Didier Legat, Philippe Manet, 2005 .

Investigation of Monostable-Bistable Transition Logic Element Circuits based on Ultra-Low-Power Diodes

David Bol, Denis Flandre, Jean-Didier Legat, 2006 .

Automatic HDL code generation for system-level design

Jean-Didier Legat, Bertrand Rousseau, Philippe Manet, 2006 .

Bulk vs SOI CMOS APS optimal design for low power low voltage applications

Denis Flandre, Jean-Didier Legat, Aryan Afzalian, 2001 .

A near-threshold instruction cache with zero miss overhead time for dual-Vdd microcontrollers

David Bol, Cédric Hocquet, François Botman, 2011 .

Parallel implementations of the RCE algorithm

Jean-Didier Legat, Philippe Thissen, Jean-Luc Voz, 1994 .

Hardware implementation of a fingerprinting algorithm suited for digital cinema

Jean-Didier Legat, Benoit M. Macq, Jean-Jacques Quisquater, 2004, 2004 12th European Signal Processing Conference.

Fine grain parallelization of multibody system equations of motion

Jean-Didier Legat, Paul Fisette, Tony Postiau, 1999, PARCO.

A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2003, FPGA '03.

Comparaison des logiques différentielles à faible consommation et à amplitude réduite

Jean-Didier Legat, 2003 .

A new mechanism to reduce congestion on TDM networks-on-chips

Jean-Didier Legat, Angelo Kuti Lusala, Daniel Vergeylen, 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels

David Bol, Denis Flandre, Jean-Didier Legat, 2010, TODE.

A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002, CHES.

The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic

David Bol, Denis Flandre, Jean-Didier Legat, 2010, 2010 Proceedings of ESSCIRC.

Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit

Jean-Didier Legat, Olivier Cantineau, Laurent Petit, 1998, J. VLSI Signal Process..

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications

David Bol, Jean-Didier Legat, Philippe Manet, 2005, PATMOS.

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas

David Bol, Jean-Didier Legat, Charlotte Frenkel, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

A dedicated DSP architecture for discrete wavelet transform

Jean-Didier Legat, Pierre Desneux, 2000, Integr. Comput. Aided Eng..

Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns

Michel Verleysen, Jean-Didier Legat, Philippe Thissen, 1993, IWANN.

New multilevel parallelism management for multimedia processors

Jean-Didier Legat, Benoît Macq, Jean-Jacques Quisquater, 1998, Electronic Imaging.

Modeling the impact of bitstreams transfer in dynamically reconfigurable platforms

Jean-Didier Legat, Hans Vandierendonck, Bertrand Rousseau, 2008 .

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs

Jean-Didier Legat, Angelo Kuti Lusala, Renaud Van Langendonck, 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

Design of an IP-Based Modular Architecture for an MPEG-2 Video Decoding Circuit

Jean-Didier Legat, Laurent Petit, 1998 .

Handwritten digit recognition by suboptimal bayesian classifier

Jean-Didier Legat, Philippe Thissen, Jean-Luc Voz, 1994 .

A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations

David Bol, Jean-Didier Legat, Alexandre Valentian, 2014, J. Low Power Electron..

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits

David Bol, Denis Flandre, Jean-Didier Legat, 2009, ISLPED.

Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

Study of Parallelism between memory accesses for multi-bank architectures

Jean-Didier Legat, Hans Vandierendonck, Philippe Manet, 2006 .

Development of Multimedia Tools based on Java applets for teaching electrical circuits basics during the first year physic course at UCL

Jean-Didier Legat, Francis Labrique, Sophie Labrique, 2002 .

A Graph-Oriented Task Manager for Small Multiprocessor Systems

Jean-Didier Legat, Benoit M. Macq, Jean-Jacques Quisquater, 1999, Euro-Par.

A low-power multiprocessor architecture for embedded reconfigurable systems

Jean-Didier Legat, Christophe Amerijckx, 1998 .

Reconfigurable hardware solutions for the digital rights management of digital cinema

Jean-Didier Legat, Benoit M. Macq, Jean-Jacques Quisquater, 2004, DRM '04.

Architecture of a reconfigurable system based on an embedded FPPA

Jean-Didier Legat, Christophe Amerijckx, 1998, Other Conferences.