Liqiong Wei

发表

Vertically integrated SOI circuits for low-power and high-performance applications

Kaushik Roy, Liqiong Wei, Rongtian Zhang, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, ISLPED '98.

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

James Tschanz, Vivek De, Shekhar Y. Borkar, 2002, DAC '02.

Low voltage low power CMOS design techniques for deep submicron ICs

Kaushik Roy, Vivek De, Liqiong Wei, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Kaushik Roy, Liqiong Wei, Zhanping Chen, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions

Kaushik Roy, Ali Keshavarzi, Liqiong Wei, 2002, IEEE Design & Test of Computers.

Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

Kaushik Roy, Liqiong Wei, Z. Chen, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Mark C. Johnson, Kaushik Roy, Vivek De, 1999, IEEE Trans. Very Large Scale Integr. Syst..

High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Kaushik Roy, Liqiong Wei, Naran Sirisantana, 2000, Proceedings 2000 International Conference on Computer Design.

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

Ying Zhang, Kevin Zhang, Pramod Kolar, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

REDUCING GLITCHING AND LEAKAGE POWER IN LOW VOLTAGE CMOS CIRCUITS

Kaushik Roy, Liqiong Wei, Zhanping Chen, 1997 .

Low-voltage and high-speed CMOS/SIMOX technology

Liqiong Wei, Xuemei Xi, Yangyuan Wang, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

General drain current model for double-gate SOl MOSFET

Liqiong Wei, Zhanping Chen, Mingzhen Xu, 1996 .

Design and optimization of low voltage high performance dual threshold CMOS circuits

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Pramod Kolar, Uddalak Bhattacharya, Fatih Hamzaoglu, 2011, IEEE Design & Test of Computers.

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

J. Tschanz, Liqiong Wei, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques

Kaushik Roy, Liqiong Wei, Zhanping Chen, 2001, IEEE Trans. Very Large Scale Integr. Syst..

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist

John Keane, Eric Karl, Uddalak Bhattacharya, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Design and optimization of multiple threshold CMOS for low power and high performance applications

Liqiong Wei, 1999 .

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

Ying Zhang, Kevin Zhang, Pramod Kolar, 2010, IEEE Journal of Solid-State Circuits.

Experimental investigation on degradation effects in fully depleted SIMOX/SOI MOSFET's induced by single transistor latch

Yuhua Cheng, Liqiong Wei, Yangyuan Wang, 1995 .

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Kaushik Roy, Vivek De, Liqiong Wei, 1999, DAC '99.

A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Pramod Kolar, Uddalak Bhattacharya, Fatih Hamzaoglu, 2008, IEEE Journal of Solid-State Circuits.

Design and optimization for low-leakage with multiple threshold CMOS

Kaushik Roy, Liqiong Wei, 1998 .

Multiple Vth CMOS for Leakage Control in Deep Submicron IC's

Kaushik Roy, Liqiong Wei, 1998 .