Teresa Monreal Arnal

发表

An adaptive controller to save dynamic energy in LP-NUCA

Dario Suarez Gracia, Teresa Monreal Arnal, Víctor Viñals Yúfera, 2011 .

A comparison of cache hierarchies for SMT processors

Dario Suarez Gracia, Teresa Monreal Arnal, Víctor Viñals Yúfera, 2011 .

STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption

Teresa Monreal Arnal, Víctor Viñals Yúfera, Carlos Escuín Blasco, 2019 .

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping

Víctor Viñals, Teresa Monreal Arnal, Darío Suárez Gracia, 2014, TACO.

Microarchitectural Support for Speculative Register Renaming

Mateo Valero, Víctor Viñals, Teresa Monreal Arnal, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

Francisco J. Cazorla, Mateo Valero, Víctor Viñals, 2008, 2008 20th International Symposium on Computer Architecture and High Performance Computing.

Late allocation and early release of physical registers

Mateo Valero, José González, Víctor Viñals, 2004, IEEE Transactions on Computers.

Light NUCA: a proposal for bridging the inter-cache latency gap

Víctor Viñals, Ramón Beivide, Teresa Monreal Arnal, 2009, DATE '09.

ReD: A policy based on reuse detection for demanding block selection in last-level Caches

Teresa Monreal Arnal, Víctor Viñals Yúfera, José María Llaberia Griño, 2017 .

Hardware support for early register release

Mateo Valero, Víctor Viñals, Teresa Monreal Arnal, 2005, Int. J. High Perform. Comput. Netw..

Virtual registers

Mateo Valero, José González, Teresa Monreal Arnal, 1997, Proceedings Fourth International Conference on High-Performance Computing.

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors

Giorgos Dimitrakopoulos, Víctor Viñals, Teresa Monreal Arnal, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reuse Detector: Improving the Management of STT-RAM SLLCs

Manuel Prieto, Luis Piñuel, Víctor Viñals, 2018, Comput. J..

Dynamic Register Renaming Through Virtual-Physical Registers

Mateo Valero, José González, Víctor Viñals, 2000, J. Instr. Level Parallelism.

ReD: A reuse detector for content selection in exclusive shared last-level caches

Javier Díaz, Víctor Viñals, José María Llabería, 2019, J. Parallel Distributed Comput..

A fault-tolerant last level cache for CMPs operating at ultra-low voltage

Víctor Viñals, Teresa Monreal Arnal, Darío Suárez Gracia, 2019, J. Parallel Distributed Comput..

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Víctor Viñals, Teresa Monreal Arnal, Alexandra Ferrerón-Labari, 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.

Speculative early register release

Mateo Valero, Víctor Viñals, Teresa Monreal Arnal, 2006, CF '06.

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Teresa Monreal Arnal, Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, 2016, IEEE Transactions on Computers.

Delaying physical register allocation through virtual-physical registers

Mateo Valero, José González, Víctor Viñals, 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

Hardware schemes for early register release

Mateo Valero, Víctor Viñals, Teresa Monreal Arnal, 2002, Proceedings International Conference on Parallel Processing.

Near-optimal replacement policies for shared caches in multicore processors

Víctor Viñals, José María Llabería, Teresa Monreal Arnal, 2021, The Journal of Supercomputing.