Alexander Sudnitson

发表

Web-Based Software Implementation of Finite State Machine Decomposition for Design and Education

Sergei Devadze, Margus Kruus, Alexander Sudnitson, 2001 .

Methodology and international collaboration in teaching reconfigurable systems

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2012, Proceedings of the 2012 IEEE Global Engineering Education Conference (EDUCON).

Fast Processing of Non-Repeated Values in Hardware

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2017 .

Application of extensible processing platforms for experiments with FPGA-based circuits

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2014, MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference.

Hardware implementation of recursive sorting algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA).

FPGA-based systems in information and communication

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 5th International Conference on Application of Information and Communication Technologies (AICT).

Hardware accelerators for information retrieval and data mining

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2015, 2015 International Conference on Information and Communication Technology Research (ICTRC).

Computational kernel extraction for synthesis of power-managed sequential components

Alexander Sudnitson, A. Sudnitson, 2002, 9th International Conference on Electronics, Circuits and Systems.

Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

Hardware implementation of recursive algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Integration of high-level synthesis to the courses on reconfigurable digital systems

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2015, 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

Acceleration of Recursive Data Sorting over Tree-based Structures

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011 .

Processing Sorted Subsets in a Multi-level Reconfigurable Computing System

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2015 .

Teaching FPGA-based systems

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2014, 2014 IEEE Global Engineering Education Conference (EDUCON).

Processing N-ary trees in hardware circuits

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 International Symposium on Integrated Circuits.

Project-Oriented Approach to Low-Power Topics in Advanced Digital Design Course

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2010 .

Application-specific hardware accelerator for implementing recursive sorting algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Field-Programmable Technology.

RAM-based mergers for data sort and frequent item computation

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2017, 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

Implementation in FPGA of Address-Based Data Sorting

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Solving Computationally Intensive Problems in Reconfigurable Hardware:A Case Study

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2013 .

Web-based system for sequential machines decomposition

Margus Kruus, Alexander Sudnitson, S. Devadze, 2003, The IEEE Region 8 EUROCON 2003. Computer as a Tool..

Address-based data processing over N-ary trees

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2013, Eurocon 2013.

Fast Data Sort Based on Searching Networks with Ring Pipeline

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2016 .

FPGA-based time and cost effective Hamming weight comparators for binary vectors

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2015, IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON).

Low power synthesis based on information theoretic measures

Alexander Sudnitson, E. Fomina, A. Keevallik, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

Optimization of recursive sorting algorithms for implementation in hardware

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Microelectronics.

Design space exploration in multi-level computing systems

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2014, CompSysTech.

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2017 .

Performance evaluation for FPGA-based processing of tree-like structures

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Hardware Implementation of Recursive Sorting Algorithms Using Tree-like Structures and HFSM Models. Rekursiivsete sortimisalgoritmide riistvaraline realiseerimine kasutades puulaadseid struktuure ja HFSM mudeleid

Alexander Sudnitson, Valeri Sklyarov, 2012 .

FSM decomposition with application to FPGA synthesis

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2009, CompSysTech '09.

A decomposition procedure for register-transfer level power management

Margus Kruus, Alexander Sudnitson, Elena Fomina, 2003, CompSysTech '03.

Implementation of address-based data sorting on different FPGA platforms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, East-West Design & Test Symposium (EWDTS 2013).

FPGA platform based digital design education

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2008, CompSysTech.

Advanced topics of FSM design using FPGA educational boards and web-based tools

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Asynchronous e-learning resources for hardware design issues

Raimund Ubar, Heinz-Dietrich Wuttke, Artur Jutman, 2004, CompSysTech '04.

High-performance hardware accelerators for sorting and managing priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Recursion and hierarchy in digital design and prototyping: a case study

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2011, CompSysTech '11.

Fast Matrix Covering in All Programmable Systems-on-Chip

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2014 .

FPGA-based Accelerators for Parallel Data Sort

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2014, Appl. Comput. Syst..

Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2016, 2016 18th Mediterranean Electrotechnical Conference (MELECON).

Optimization of address-based data sorting unit with external memory support

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, CompSysTech '13.

Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2015, 2015 Euromicro Conference on Digital System Design.

Reconfigurable systems in engineering education: Best practices and future trends

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2017, 2017 IEEE Global Engineering Education Conference (EDUCON).

Using SAT-Based Techniques in Low Power State Assignment

Alexander Sudnitson, Fadi A. Aloul, Assim Sagahyroon, 2011, J. Circuits Syst. Comput..

Processing N-ary trees in reconfigurable hardware

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, 2013 25th International Conference on Microelectronics (ICM).

Implementation of parallel operations over streams in extensible processing platforms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Processing tree-like data structures for sorting and managing priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 IEEE Symposium on Computers & Informatics.

Web Based Tools for Synthesis and Testing of Digital Devices

Raimund Ubar, Sergei Devadze, Margus Kruus, 2002 .

Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2016, Int. J. Comput. Commun. Control.

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

and Managing Priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011 .

Using mobile technology to enhance teaching reconfigurable systems

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2013, Proceedings of 2013 IEEE International Conference on Teaching, Assessment and Learning for Engineering (TALE).

Multilevel models for data processing

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 IEEE GCC Conference and Exhibition (GCC).

Synthesis of Sequential Circuits with Dynamic Power Management

Margus Kruus, Alexander Sudnitson, Harri Lensen, 2005 .

Low power state assignment using ILP techniques

Alexander Sudnitson, Fadi A. Aloul, Assim Sagahyroon, 2010, Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference.