Kaviraj Chopra

发表

Statistical technology mapping for parametric yield

David Blaauw, Kaviraj Chopra, A. Singh, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Circuit optimization using statistical static timing analysis

David Blaauw, Vladimir Zolotov, Aseem Agarwal, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis

David Blaauw, Dennis Sylvester, Cheng Zhuo, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States

Sarma B. K. Vrudhula, Kaviraj Chopra, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analysis and Modeling of CD Variation for Statistical Static Timing

David Blaauw, Yu Cao, Brian Cline, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

A new statistical max operation for propagating skewness in statistical timing analysis

David Blaauw, Bo Zhai, Dennis Sylvester, 2006, ICCAD.

MONSOON Image Acquisition System

Michael Warner, Kaviraj Chopra, Charles F. Claver, 2004 .

A framework for battery-aware sensor management

Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Fast Statistical Static Timing Analysis Using Smart

David Blaauw, Dennis Sylvester, Vineeth Veetil, 2011 .

Statistical Performance Analysis Optimization of Digital Circuits

David Blaauw, Kaviraj Chopra, K. Chopra, 2008 .

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

David Blaauw, Dennis Sylvester, Ashish Srivastava, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Statistical timing based optimization using gate sizing

David Blaauw, Aseem Agarwal, Kaviraj Chopra, 2005, Design, Automation and Test in Europe.

A statistical approach for full-chip gate-oxide reliability analysis

David Blaauw, Dennis Sylvester, Cheng Zhuo, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

CAD tools for variation tolerance

David Blaauw, Kaviraj Chopra, 2005, DAC '05.

Victim Alignment in Crosstalk-Aware Timing Analysis

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance

David Blaauw, Dennis Sylvester, Ashish Srivastava, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Statistical Timing Analysis: From Basic Principles to State of the Art

David Blaauw, Ashish Srivastava, Kaviraj Chopra, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Top-k Aggressors Sets in Delay Noise Analysis

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Victim alignment in crosstalk aware timing analysis

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2007, ICCAD 2007.

Implicit pseudo boolean enumeration algorithms for input vector control

Sarma B. K. Vrudhula, Kaviraj Chopra, 2004, Proceedings. 41st Design Automation Conference, 2004..

Victim Alignment in Crosstalk-Aware Timing Analysis

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Kaviraj Chopra, 2004, 17th International Conference on VLSI Design. Proceedings..

An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits

David Blaauw, Dennis Sylvester, Kaviraj Chopra, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques

David Blaauw, Dennis Sylvester, Vineeth Veetil, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Transistor-Specific Delay Modeling for SSTA

David Blaauw, Brian Cline, Savithri Sundareswaran, 2008, 2008 Design, Automation and Test in Europe.

A statistical approach for full-chip gate-oxide reliability analysis

David Blaauw, Dennis Sylvester, Cheng Zhuo, 2008, ICCAD 2008.

Current Source Driver Model Synthesis and Worst-case Alignment for Accurate Timing and Noise Analysis

David Blaauw, Kaviraj Chopra, Haihua Su, 2006 .

Timing Based Optimization using Gate Sizing

David Blaauw, Aseem Agarwal, Kaviraj Chopra, 2002 .

Variogram based Robust Extraction of Process Variation Model

David Blaauw, Kaviraj Chopra, Narendra Shenoy, 2007 .