Gerald R. Morris

发表

An FPGA-based floating-point Jacobi iterative solver

Viktor K. Prasanna, Gerald R. Morris, 2005, 8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05).

Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-7 High Performance Reconfigurable Computer

Khalid H. Abed, Gerald R. Morris, 2010, 2010 DoD High Performance Computing Modernization Program Users Group Conference.

Accelerating a Sparse Matrix Iterative Solver Using a High Performance Reconfigurable Computer

Khalid H. Abed, Gerald R. Morris, Ricky Y. McGruder, 2010, 2010 DoD High Performance Computing Modernization Program Users Group Conference.

Designing scalable FPGA-based reduction circuits using pipelined floating-point cores

Viktor K. Prasanna, Gerald R. Morris, Ling Zhuo, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Improving Performance of Codes with Large/Irregular Stride Memory Access Patterns via High Performance Reconfigurable Computers

Khalid H. Abed, Gerald R. Morris, 2009, HiPC 2009.

Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers

Khalid H. Abed, Gerald R. Morris, G. R. Morris, 2013, J. Comput..

An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets

Viktor K. Prasanna, Gerald R. Morris, Richard D. Anderson, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer

Viktor K. Prasanna, Gerald R. Morris, V. Prasanna, 2008, J. Parallel Distributed Comput..

Matrix putations on configurable Hardware

Viktor K. Prasanna, Gerald R. Morris, 2007 .

Integrating Quartus Wizard-based VHDL floating-point components into a high performance heterogeneous computing environment

Khalid H. Abed, Gerald R. Morris, Nikeya S. Peay, 2011, 2011 Proceedings of IEEE Southeastcon.

Sparse Matrix Computations on Reconfigurable Hardware

Viktor K. Prasanna, Gerald R. Morris, 2007, Computer.

Mapping a Jacobi Iterative Solver onto a High-Performance Heterogeneous Computer

Khalid H. Abed, Gerald R. Morris, G. R. Morris, 2013, IEEE Transactions on Parallel and Distributed Systems.

A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer

Viktor K. Prasanna, Gerald R. Morris, Richard D. Anderson, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Achieving true parallelism on a High Performance Heterogeneous Computer via a threaded programming model

Khalid H. Abed, Gerald R. Morris, Antoinette R. Anderson, 2011, 2011 Proceedings of IEEE Southeastcon.

Improving Performance of Codes with Large/Irregular Stride Memory Access Patterns via High Performance Reconfigurable Computers

Khalid H. Abed, Gerald R. Morris, G. R. Morris, 2009, 2009 DoD High Performance Computing Modernization Program Users Group Conference.

High-performance FPGA-based general reduction methods

Viktor K. Prasanna, Gerald R. Morris, Ling Zhuo, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers

Khalid H. Abed, Gerald R. Morris, Justin L. Rice, 2009, J. Comput..

Mapping sparse matrix scientific applications onto fpga-augmented reconfigurable supercomputers

Viktor K. Prasanna, Gerald R. Morris, 2006 .

High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs

Viktor K. Prasanna, Gerald R. Morris, Ling Zhuo, 2007, IEEE Transactions on Parallel and Distributed Systems.

FPGA-based implementation of Horner's rule on a high performance heterogeneous computer

Khalid H. Abed, Gerald R. Morris, Ales-cia N. Malone, 2011, 2011 Proceedings of IEEE Southeastcon.