R. Arghavani

R-1: Navigating the Roadmap to 32nm and Beyond: Breaking the Barriers

T. Skotnicki, S. Inaba, R. Arghavani, 2007, 2007 IEEE Symposium on VLSI Technology.

Scalability of partially depleted SOI technology for sub-0.25 /spl mu/m logic applications

P. Packan, M. Alavi, D. Douglas, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Impact of contact and local interconnect scaling on logic performance

S. Datta, R. Arghavani, R. Pandey, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Wen-Chin Lee, S. Demuynck, Jianxin Lei, 2008, IEEE Transactions on Electron Devices.

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing

G. Karunasiri, R. Arghavani, H. M'Saad, 2006, IEEE Electron Device Letters.

A 50 nm depleted-substrate CMOS transistor (DST)

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Analysis of local interconnect resistance at scaled process nodes

S. Datta, R. Arghavani, R. Pandey, 2015, 2015 73rd Annual Device Research Conference (DRC).

Will strong quantum confinement effect limit low VCC logic application of III–V FINFETs?

S. Datta, A. Nidhi, R. Arghavani, 2012, 70th Device Research Conference.