Vivek Chickermane

发表

Channel masking synthesis for efficient on-chip test compression

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2004, 2004 International Conferce on Test.

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Jeongho Cho, Vivek Chickermane, Brion L. Keller, 2013, 2013 IEEE International Test Conference (ITC).

Efficient testing of hierarchical core-based SOCs

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2014, 2014 International Test Conference.

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2009, 2009 Asian Test Symposium.

Automating IEEE 1500 Core Test—An EDA Perspective

Vivek Chickermane, Krishna Chakravadhanula, 2009, IEEE Design & Test of Computers.

System-on-Chip Testability Using LSSD Scan Structures

Vivek Chickermane, Shambhu J. Upadhyaya, Kamran Zarrineh, 2001, IEEE Des. Test Comput..

Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications

Vivek Chickermane, Brian Foutz, Krishna Chakravadhanula, 2019, 2019 IEEE International Test Conference (ITC).

APT: an area-performance-testability driven placement algorithm

Janak H. Patel, Vivek Chickermane, Sungho Kim, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Automation of 3D-DfT Insertion

Mario H. Konijnenburg, Vivek Chickermane, Brion L. Keller, 2011, 2011 Asian Test Symposium.

Non-Scan Design-for-Testability Techniques for Sequential Circuits

Elizabeth M. Rudnick, Janak H. Patel, Vivek Chickermane, 1993, 30th ACM/IEEE Design Automation Conference.

Addressing early design-for-test synthesis in a production environment

Vivek Chickermane, Kamran Zarrineh, 1997, Proceedings International Test Conference 1997.

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2012, 2012 IEEE International Test Conference.

Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium

Vivek Chickermane, Peilin Song, Stefano Di Carlo, 2020, IEEE Des. Test.

Channel masking synthesis for efficient on-chip test compression

Vivek Chickermane, Brion Keller, Brian Edward Foutz, 2004 .

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults

Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

A building block BIST methodology for SOC designs: a case study

Vivek Chickermane, Patrick R. Gallagher, Steven Gregor, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

An observability enhancement approach for improved testability and at-speed test

Elizabeth M. Rudnick, Janak H. Patel, Vivek Chickermane, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SmartScan - Hierarchical test compression for pin-limited low power designs

Vivek Chickermane, Subhasish Mukherjee, Krishna Chakravadhanula, 2013, 2013 IEEE International Test Conference (ITC).

Advancing test compression to the physical dimension

Vivek Chickermane, Brian Foutz, David Scott, 2017, 2017 IEEE International Test Conference (ITC).

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

Vivek Chickermane, Brion L. Keller, Anis Uzzaman, 2005, 14th Asian Test Symposium (ATS'05).

Design for Testability Using Architectural Descriptions

Janak H. Patel, Vivek Chickermane, Jaushin Lee, 1992, Proceedings International Test Conference 1992.

Addressing design for testability at the architectural level

Janak H. Patel, Vivek Chickermane, Jaushin Lee, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An optimization based approach to the partial scan design problem

Janak H. Patel, Vivek Chickermane, J. Patel, 1990, Proceedings. International Test Conference 1990.

A comparative study of design for testability methods using high-level and gate-level descriptions

Janak H. Patel, Vivek Chickermane, Jaushin Lee, 1992, ICCAD.

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Test Generation for State Retention Logic

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2008, 2008 17th Asian Test Symposium.

Innovative practices session 1C: Existing/emerging low power techniques

Nilanjan Mukherjee, Wei Zhao, Vivek Chickermane, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

3D design‐for‐test architecture

Mario Konijnenburg, Vivek Chickermane, Erik Jan Marinissen, 2019 .

Practical Aspects of Delay Testing for Nanometer Chips

Vivek Chickermane, Brion L. Keller, Anis Uzzaman, 2005, 14th Asian Test Symposium (ATS'05).

A fault oriented partial scan design approach

Janak H. Patel, Vivek Chickermane, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Capture power reduction using clock gating aware test generation

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2009, 2009 International Test Conference.

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Vivek Chickermane, Krishna Chakravadhanula, James Sage, 2008, 2008 IEEE International Test Conference.

Restructuring VLSI layout representations for efficiency

Vivek Chickermane, Ravi Nair, Ray Chamberlain, 1991, Proceedings of the European Conference on Design Automation..

Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study

Vivek Chickermane, Erik Jan Marinissen, Sandeep Kumar Goel, 2019 .

International TestConference 2008 Technical Program Committee

Abhijit Chatterjee, Kenneth M. Butler, Cecilia Metra, 2008 .

A design for test perspective on I/O management

Vivek Chickermane, Gareth Nicholls, Kamran Zarrineh, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2010, 2010 IEEE International Test Conference.

Sequential circuit testability enhancement using a nonscan approach

Elizabeth M. Rudnick, Janak H. Patel, Vivek Chickermane, 1995, IEEE Trans. Very Large Scale Integr. Syst..

An economic analysis and ROI model for nanometer test

Vivek Chickermane, Brion Keller, M. Tegethoff, 2004 .

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2013, 2013 18th IEEE European Test Symposium (ETS).

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures

Vivek Chickermane, Krishna Chakravadhanula, Sameer Chillarige, 2015, 2015 IEEE 24th North Atlantic Test Workshop.

Impact of high level functional constraints on testability

Janak H. Patel, Vivek Chickermane, Jaushin Lee, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

An economic analysis and ROI model for nanometer test

Vivek Chickermane, Brion L. Keller, Mick Tegethoff, 2004, 2004 International Conferce on Test.

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices

Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula, 2014, VLSI Design.

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, IEEE Design & Test.