Brion L. Keller

发表

Channel masking synthesis for efficient on-chip test compression

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2004, 2004 International Conferce on Test.

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Jeongho Cho, Vivek Chickermane, Brion L. Keller, 2013, 2013 IEEE International Test Conference (ITC).

Efficient testing of hierarchical core-based SOCs

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2014, 2014 International Test Conference.

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2009, 2009 Asian Test Symposium.

Using STIL to describe embedded core test requirements

Brion L. Keller, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A Partially-Exhaustive Gate Transition Fault Model

Brion L. Keller, Anis Uzzaman, Richard Billings, 2009, 2009 Asian Test Symposium.

Delay Test: The Next Frontier for LSSD Test Systems

Brion L. Keller, T. Williams, Barry K. Rosen, 1992, Proceedings International Test Conference 1992.

A SmartBIST variant with guaranteed encoding

Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, 2001, Proceedings 10th Asian Test Symposium.

Automation of 3D-DfT Insertion

Mario H. Konijnenburg, Vivek Chickermane, Brion L. Keller, 2011, 2011 Asian Test Symposium.

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2012, 2012 IEEE International Test Conference.

Design and implementation of a parallel weighted random pattern and logic built in self test algorithm

Brion L. Keller, Paul Chang, Sarala Paliwal, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Extending OPMISR beyond 10x Scan Test Efficiency

Brion L. Keller, David Scott, Andrew Ferko, 2002, IEEE Des. Test Comput..

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test

Masayuki Arai, Brion L. Keller, Kazuhiko Iwasaki, 2009, J. Low Power Electron..

CTL the language for describing core-based test

Rohit Kapur, Brion L. Keller, Maurice Lousberg, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

The compiled logic simulator

Brion L. Keller, William Maloney, David P. Carlson, 1991, IEEE Design & Test of Computers.

Test methodologies and design automation for IBM ASICs

Brion L. Keller, Pamela S. Gillis, Tom S. Guzowski, 1996, IBM J. Res. Dev..

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

Vivek Chickermane, Brion L. Keller, Anis Uzzaman, 2005, 14th Asian Test Symposium (ATS'05).

CTL and Its Usage in the EDA Industry

Rohit Kapur, Brion L. Keller, Sandeep Bhatia, 2009, IEEE Design & Test of Computers.

OCI: Open Compression Interface

Rohit Kapur, Brion L. Keller, Benoit Nadeau-Dostie, 2006, 2006 IEEE International Test Conference.

Effective parallel processing techniques for the generation of test data for a logic built-in self test system

Brion L. Keller, Paul Chang, Sarala Paliwal, 2000, Proceedings of the Ninth Asian Test Symposium.

Test Generation for State Retention Logic

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2008, 2008 17th Asian Test Symposium.

Use of MISRs for compression and diagnostics

Brion L. Keller, Thomas Bartenstein, 2005, IEEE International Conference on Test, 2005..

Practical Aspects of Delay Testing for Nanometer Chips

Vivek Chickermane, Brion L. Keller, Anis Uzzaman, 2005, 14th Asian Test Symposium (ATS'05).

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Capture power reduction using clock gating aware test generation

Vivek Chickermane, Brion L. Keller, Krishna Chakravadhanula, 2009, 2009 International Test Conference.

OPMISR: the foundation for compressed ATPG vectors

Brion L. Keller, Owen Farnsworth, Andrej Ferko, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2010, 2010 IEEE International Test Conference.

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Brion L. Keller, Gary Grise, Thomas J. Snethen, 2007, 2007 IEEE International Test Conference.

High performance parallel fault simulation

Bapiraju Vinnakota, Brion L. Keller, Amit K. Varshney, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Encounter test OPMISR/sup +/ on-chip compression

Brion L. Keller, 2005, IEEE International Conference on Test, 2005..

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2013, 2013 18th IEEE European Test Symposium (ETS).

Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count

Brion L. Keller, Richard Schoonover, Robert Butler, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression

Masayuki Arai, Brian Foutz, Brion L. Keller, 2010, IEICE Trans. Inf. Syst..

An economic analysis and ROI model for nanometer test

Vivek Chickermane, Brion L. Keller, Mick Tegethoff, 2004, 2004 International Conferce on Test.

Optimizing Test Data Volume Using Hybrid Compression

Brian Foutz, Brion L. Keller, Anis Uzzaman, 2008, 2008 17th Asian Test Symposium.

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, IEEE Design & Test.