Y. Tateshita

A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation

S. Iida, Y. Sakano, T. Asatsuma, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Three-dimensional structures for high saturation signals and crosstalk suppression in 1.20 μm pixel back-illuminated CMOS image sensor

Y. Tateshita, T. Hirayama, S. Arakawa, 2013, 2013 IEEE International Electron Devices Meeting.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Y. Tateshita, S. Kanda, N. Nagashima, 2006, 2006 International Electron Devices Meeting.

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Y. Tateshita, N. Nagashima, H. Wakabayashi, 2009, IEEE Transactions on Electron Devices.