Markus Wedler

发表

Normalization at the arithmetic bit level

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Coverage of compositional property sets under reactive constraints

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2014, Fifteenth International Symposium on Quality Electronic Design.

Arithmetic reasoning in DPLL-based SAT solving

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Structural FSM traversal

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Formal plausibility checks for environment constraints

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2012, Proceeding of the 2012 Forum on Specification and Design Languages.

Proof logging for computer algebra based SMT solving

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface

Rainer Leupers, Gerd Ascheid, Andreas Hoffmann, 2015, 2015 Forum on Specification and Design Languages (FDL).

Compositional Completeness over reactive Constraints

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2013, MBMV.

Formal hardware/software co-verification by interval property checking with abstraction

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2008, CAV.

Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors

Norbert Wehn, Markus Wedler, Dominik Stoffel, 2012 .

Modeling of custom-designed arithmetic components for ABL normalization

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2008, 2008 Forum on Specification, Verification and Design Languages.

Improving structural FSM traversal by constraint-satisfying logic simulation

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

Towards the impact of state encoding on induction-based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2003, MBMV.

A New Formal Verification Approach for Hardware-dependent Embedded System Software

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2008, FDL.

Using RTL statespace information and state encoding for induction based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Arithmetic Constraints in SAT-based Property Checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2007, MBMV.

A re-use methodology for formal SoC protocol compliance verification

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2009, 2009 Forum on Specification & Design Languages (FDL).

Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

System verification of concurrent RTL modules by compositional path predicate abstraction

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2012, DAC Design Automation Conference 2012.

Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface

Rainer Leupers, Gerd Ascheid, Andreas Hoffmann, 2015 .

Solving hard instances in QF-BV combining Boolean reasoning with computer algebra

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2009, Algorithms and Applications for Next Generation SAT Solvers.

Property Checking with Constraint Integer Programming

Markus Wedler, Tobias Achterberg, Raik Brinkmann, 2007 .

Analyzing k-step induction to compute invariants for SAT-based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2010, Design Automation Conference.

Transition-by-transition FSM traversal for reachability analysis in bounded model checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Path predicate abstraction by complete interval property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2010, Formal Methods in Computer Aided Design.

Frontend model generation for SAT-based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2005, 2005 6th International Conference on ASIC.

Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking

Norbert Wehn, Markus Wedler, Wolfgang Kunz, 2008, 2008 Symposium on Application Specific Processors.

STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2011, 2011 Design, Automation & Test in Europe.

A case study on applying bounded model checking to analog circuit verification

Markus Wedler, Wolfgang Kunz, Lars Hedrich, 2006, MBMV.

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Markus Wedler, Wolfgang Kunz, Matthias Pflanz, 2008, 2008 Asia and South Pacific Design Automation Conference.

A Re-Use Methodology for SoC Protocol Compliance Verification

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2009, MBMV.

A Normalization Method for Arithmetic Data-Path Verification

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Formale Verifikation einer Hardware-Implementierung des LIN-Protokoll Kontrollers

Markus Wedler, Bernard Schmidt, Katharina Weinberger, 2008, MBMV.

Exploiting state encoding for invariant generation in induction-based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Complete Verification of Weakly Programmable IPs against Their Operational ISA Model

Norbert Wehn, Markus Wedler, Dominik Stoffel, 2010, FDL.

Exploiting state encoding for invariant generation in induction-based property checking

Markus Wedler, Dominik Stoffel, Wolfgang Kunz, 2004 .