J. DeBrosse

A high-speed 128-kb MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2004, IEEE Journal of Solid-State Circuits.

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

G. Daniel, D. Hanson, M. Wordeman, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ

P. Poechmueller, M. Yoshida, J. DeBrosse, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

W. J. Gallagher, T. Torng, J. DeBrosse, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A high-speed 128 Kbit MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 16Mb MRAM featuring bootstrapped write drivers

H. Hoenigschmid, G. Mueller, W.J. Gallagher, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 16-Mb MRAM featuring bootstrapped write drivers

H. Hoenigschmid, G. Mueller, W.J. Gallagher, 2005, IEEE Journal of Solid-State Circuits.