Mine Toshiyuki

A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention

Takahashi Yasuhiko, Iwamatsu Toshiaki, Ishii Tomoyuki, 2008 .

Phase-change memoy driven by poly-Si transistor enabling three-dimensional stacking

Minemura Hiroyuki, Kobayashi Takashi, Takahashi Toshikazu, 2011 .