Sano Toshiaki

A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention

Takahashi Yasuhiko, Iwamatsu Toshiaki, Ishii Tomoyuki, 2008 .

A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time

Tanaka Shinji, Morimoto Masao, Nii Koji, 2017 .