Akiyama Satoru

A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention

Takahashi Yasuhiko, Iwamatsu Toshiaki, Ishii Tomoyuki, 2008 .

A Memory Controller that Reduces Latency of Cached SDRAM

Miura Seiji, Akiyama Satoru, 2005 .

A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell

Kajigaya Kazuhiko, Kawahara Takayuki, Sekiguchi Tomonori, 2005 .

Statistical Integration In Multigigabit DRAM Design

Kajigaya Kazuhiko, Kawahara Takayuki, Sekiguchi Tomonori, 2005 .