Hai Zhou

Retiming for wire pipelining in system-on-chip

Chuan Lin, Hai Zhou, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

Debjit Sinha, Hai Zhou, 2004, ICCAD 2004.

Efficient octilinear Steiner tree construction based on spanning graphs

Xianlong Hong, Qi Zhu, Yang Yang, 2004 .

Gate sizing by Lagrangian relaxation revisited

Hai Zhou, Jia Wang, Debapriya Das, 2007, ICCAD 2007.

Linear constraint graph for floorplan optimization with soft blocks

Hai Zhou, Jia Wang, 2008, ICCAD 2008.

Interconnect-driven floorplanning by searching alternative packings

Chiu-wing Sham, Hai Zhou, E.F.Y. Young, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..